LF48908JC50 データシートの表示（PDF） - LOGIC Devices Incorporated

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LF48908JC50

Two Dimensional Convolver

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LF48908

Two Dimensional Convolver

SIGNAL DEFINITIONS

CASO7-0 — Cascade Output

A2-0 — Control Logic Address Lines

Power

The data presented on CASO7-0 is the A2-0 determines which Control Logic

VCC and GND

internal ALU output delayed by twice Register will receive the CIN9-0 data.

the programmed internal row buffer

+5 V power supply. All pins must be

connected.

length.

Controls

CS — Chip Select

1

When CS is LOW, data can be loaded

into the Control Logic Registers.

Clock

RESET — Reset Control

When CS is HIGH, data can not be

2

CLK — Master Clock

When RESET is LOW, all internal

loaded and the register contents will

not be changed.

The rising edge of CLK strobes all

circuitry is reset, all outputs are forced

enabled registers except for the

Control Logic Registers.

LOW, all Control Logic Registers are

loaded with their default values

LD — Load Strobe

3

(which is 0 for each one except the

If CS and LD are LOW, the data

Inputs

DIN7-0 — Pixel Data Input

ALU Microcode Register which has a present on CIN9-0 will be latched into

4

default value of “0000011000”), and all the Control Logic Register addressed

other internal registers are loaded

by A2-0 on the rising edge of LD.

DIN7-0 is the 8-bit registered pixel

with a “0”.

5

data input port. Data is latched on the

FUNCTIONAL DESCRIPTION

rising edge of CLK.

FRAME — New Frame Input Control

The LF48908, a two-dimensional

When asserted, FRAME signals the

convolver, executes convolutions using

6

CIN9-0 — Coefficient and Control Logic start of a new frame. When FRAME is internal row buffers to reduce design

Register Input

LOW, all internal circuitry is reset

complexity and board space require-

CIN7-0 is used to load the Coefficient

Registers or can be used to provide a

second operand input to the ALU.

except for the ALU Microcode, Row

Length, Initialization, Coefficient, and

ALU Registers.

ments. 8-bit image data, in raster scan,

non-interlace format, is convolved with

one of two internal, 3 x 3 user-

7

CIN8-0 is used to load the Initializa-

tion Register. CIN9-0 is used to load

EALU — Enable ALU Register Input

programable filter kernels. Two 1024 x 8-

bit row buffers provide the data delay

8

the ALU Microcode and Row Buffer

Length Registers. The Control Regis-

ter Address Lines, A2-0, determine

which register will receive the CIN

When HIGH, data on CIN7-0 is latched

into the ALU Register on the next

rising edge of CLK. When LOW, data

on CIN7-0 will not be latched into the

needed to perform two-dimensional

convolutions on a single chip. The result

output of 20-bits allows for word growth

during the convolution operation.

9

data. The CIN data is loaded into the ALU Register and the register con-

addressed register by using the CS

tents will not be changed.

10 The input data path (DIN7-0) provides

access to an 8-bit ALU. This allows

and LD control inputs.

point operations to be performed on

HOLD — Hold Control

the incoming data stream before

CASI15-0 — Cascade Input

The cascade input is used when

multiple LF48908s are cascaded

together or when external row buffers

are needed. This allows convolutions

The HOLD input is used to disable

CLK from all of the internal circuitry.

HOLD is latched on the rising edge of

CLK and takes effect on the next rising

edge of CLK. When HOLD is HIGH,

reaching the row buffers and the

convolver. The length of these buffers

is programmable for use in various

video formats without the need for

additional external delay.

11

of larger kernels or longer row sizes. CLK will have no effect on the

This device is configured by loading

LF48908 and all internal data will

the coefficent data (filter kernels) and

Outputs

remain unchanged.

row buffer length through the

DOUT19-0 — Data Output

DOUT19-0 is the 20-bit registered data

output port.

OE — Output Enable

When OE is LOW, DOUT19-0 is

enabled for output. When OE is

HIGH, DOUT19-0 is placed in a high-

impedance state.

coefficent data path (CIN7-0). Internal

registers are addressed using the A2-0

address lines. Chip Select (CS) and

Load Strobe (LD) complete the

configuration interface which may be

controlled by standard microproces-

sors without additional external logic.

Video Imaging Products

3

08/9/2000–LDS.48908-J

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