LF48908JC50 データシートの表示（PDF） - LOGIC Devices Incorporated

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LF48908JC50

Two Dimensional Convolver

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LF48908

Two Dimensional Convolver

FIGURE 4. LF48908 CONTROL LOGIC BLOCK DIAGRAM

ENCR1

3

A2-0

ENCR0

CAS

LD

ADDRESS

DECODE

CR1

1

CR0

CS

LMC

EOR

2

10

CIN9-0

LMC

ALU MICROCODE REGISTER

10

ALU MICROCODE

3

EOR

ROW LENGTH REGISTER

10

ROW LENGTH

8-0

9

9

4

CAS

INITIALIZATION REGISTER

INITIALIZATION DATA

COEFFICIENT REGISTER 0

5

7-0

8

CR0

I0

OE

H0

OE

G0

OE

F0

OE

E0

OE

D0

OE

C0

OE

B0

OE

A0

OE

6

8

8

8

8

8

8

8

8

8

I

H

G

ENCR1

SQ

F

ENCR0

RQ

E

D

C

7

B

A

7-0

8

OE

OE

OE

OE

OE

OE

OE

OE

OE

8

CR1

I1

H1

G1

F1

E1

D1

C1

B1

A1

COEFFICIENT REGISTER 1

9

through the CIN bus using A2-0, CS, Row Length Register

be loaded within 1024 CLK cycles. If

and LD (see Figure 4). All the Control

Logic Registers are set to their default

values when RESET is active. FRAME

does not affect the values in these

registers.

The value stored in the Row Length

Register determines the number of

delay stages for each row buffer. The

number of delay stages should be set

equal to the row length of the input

10 the Row Length Register is not loaded

within 1024 CLK cycles, the register

will automatically be loaded with a “0”.

Initialization Register

11

ALU Microcode Register

Operation of the ALU and shifter are

determined by the value stored in the

ALU Microcode Register. This 10-bit

instruction word is divided into two

fields. The lower seven bits define the

arithmetic and logical operations of the

ALU. The upper three bits specify shift

distance and direction. Tables 1 and 2

detail the various instruction words.

This register is loaded through CIN9-0

using the A2-0, CS, and LD controls.

Also see Arithmetic Logic Unit section.

image. The Row Length Register may

be loaded with the values 0 through

1023 (0 represents 1024 delay stages).

It is possible to program the row

buffers to have 1 or 2 delay stages, but

this will lead to meaningless results

for a 3 x 3 convolution. This register is

loaded through CIN9-0 using the A2-0,

CS, and LD controls. Once the Row

Length Register has been loaded, a

new value can not be loaded until the

LF48908 has been reset. This is done

by asserting RESET. After RESET goes

HIGH, the Row Length Register must

The Initialization Register configures

various functions of the device

including: input data delay, input

data format, coefficent data format,

output rounding, cascade mode, and

cascade input shift (see Table 3). This

register is loaded through CIN8-0

using the A2-0, CS, and LD controls.

Coefficient Registers - CREG0, CREG1

The Coefficient Registers are used to

store the filter coefficients for the

multiplier array. Each Coefficient

Video Imaging Products

5

08/9/2000–LDS.48908-J

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