LH543601M-35 データシートの表示（PDF） - Sharp Electronics

部品番号

コンポーネント説明

メーカー

LH543601M-35

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

256 × 36 × 2 Bidirectional FIFO

LH543601

OPERATIONAL DESCRIPTION (cont’d)

becomes valid on the data-bus pins (D0A – D35A or

D0B – D35B) by a time tA after the rising clock (CKA or

CKB) edge, provided that the data outputs are enabled.

OEA and OEB are assertive-LOW, asynchronous, Out-

put Enable control input signals. Their effect is only to

enable or disable the output drivers of the respective port.

Disabling the outputs does not disable a read operation;

data transmitted to the corresponding output register will

remain available later, when the outputs again are en-

abled, unless it subsequently is overwritten.

When an empty condition is reached, read operations

are locked out until a valid write operation(s) has loaded

additional data into the FIFO. Following the first write to

an empty FIFO, the corresponding empty flag (EF) will be

deasserted (HIGH). The first read operation should begin

no earlier than a First Read Latency (tFRL) after the first

write to an empty FIFO, to ensure that correct read data

words are retrieved.

Dedicated FIFO Status Flags

Six dedicated FIFO status flags are included for Full

(FF1 and FF2), Half-Full (HF1 and HF2), and Empty (EF1

and EF2). FF1, HF1, and EF1 indicate the status of FIFO

#1; and FF2, HF2, and EF2 indicate the status of FIFO #2.

A Full Flag is asserted following the first subsequent

rising clock edge for a write operation which fills the FIFO.

A Full Flag is deasserted following the first subsequent

falling clock edge for a read operation to a full FIFO. A

Half-Full Flag is updated following the first subsequent

rising clock edge of a read or write operation to a FIFO

which changes its ‘half-full’ status. An Empty Flag is

asserted following the first subsequent rising clock edge

for a read operation which empties the FIFO. An Empty

Flag is deasserted following the falling clock edge for a

write operation to an empty FIFO.

Programmable Status Flags

Four programmable FIFO status flags are provided,

two for Almost-Full (AF1 and AF2), and two for Almost-

Empty (AE1 and AE2). Thus, each port has two program-

mable flags to monitor the status of the two internal FIFO

buffer memories. The offset values for these flags are

initialized to eight locations from the respective FIFO

boundaries during reset, but can be reprogrammed over

the entire FIFO depth.

An Almost-Full Flag is asserted following the first sub-

sequent rising clock edge after a write operation which

has partially filled the FIFO up to the ‘almost-full’ offset

point. An Almost-Full Flag is deasserted following the first

subsequent falling clock edge after a read operation

which has partially emptied the FIFO down past the

‘almost-full’ offset point. An Almost-Empty Flag is as-

serted following the first subsequent rising clock edge

after a read operation which has partially emptied the

FIFO down to the ‘almost-empty’ offset point. An Almost-

Empty Flag is deasserted following the first subsequent

falling clock edge after a write operation which has par-

tially filled the FIFO up past the ‘almost-empty’ offset

point.

Flag offsets may be written or read through the Port A

data bus. All four programmable FIFO status flag offsets

can be set simultaneously through a single 36-bit status

word; or, each programmable flag offset can be set

individually, through one of four eight-bit status words.

Table 3 illustrates the data format for flag-programming

words .

Also, Table 4 defines the meaning of each of the five

flags, both the dedicated flags and the programmable

flags, for the LH543601.

WARNING: Control inputs which may affect the compu-

tation of flag values at a port generally should not change

while the clock for that port is HIGH, since some updating

of flag values takes place on the falling edge of the clock.

Mailbox Operation

Two mailbox registers are provided for passing system

hardware or software control/status words between ports.

Each port can read its own mailbox and write to the other

port’s mailbox. Mailbox access is performed on the rising

edge of the controlling FIFO’s clock, with the mailbox

address selected and the enable (ENA or ENB) HIGH.

That is, writing to Mailbox Register #1, or reading from

Mailbox Register #2, is synchronized to CKA; and writing

to Mailbox Register #2, or reading from Mailbox Register

#1, is synchronized to CKB.

The R/WA/B and OEA/B pins control the direction and

availability of mailbox-register accesses. Each mailbox

register has its own New-Mail-Alert Flag (MBF1 and

MBF2), which is synchronized to the reading port’s clock.

These New-Mail-Alert Flags are status indicators only,

and cannot inhibit mailbox-register read or write operations.

Request Acknowledge Handshake

A synchronous request-acknowledge handshake fea-

ture is provided for each port, to perform boundary syn-

chronization between asynchronously-operated ports.

The use of this feature is optional. When it is used, the

Request input (REQA/B) is sampled at a rising clock edge.

With REQA/B HIGH, R/WA/B determines whether a FIFO

read operation or a FIFO write operation is being re-

quested. The Acknowledge output (ACKA/B) is updated

during the following clock cycle(s). ACKA/B meets the

setup and hold time requirements of the Enable input

(ENA or ENB). Therefore, ACKA/B may be tied back to the

enable input to directly gate FIFO accesses, at a slight

decrease in maximum operating frequency.

The assertion of ACKA/B signifies that REQA/B was

asserted. However, ACKA/B does not depend logically on

ENA/B; and thus the assertion of ACKA/B does not prove

that a FIFO write access or a FIFO read access actually

took place. While REQA/B and ENA/B are being held

HIGH, ACKA/B may be considered as a synchronous,

predictive boundary flag. That is, ACKA/B acts as a syn-

11

Share Link: