MACH210-12JI データシートの表示（PDF） - Advanced Micro Devices
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MACH210-12JI Datasheet PDF : 51 Pages
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CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C,
VOUT = 2.0 V f = 1 MHz
AMD
Typ Unit
6
pF
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
-12
-14
Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
Setup Time from Input, I/O,
tS
or Feedback to Clock
D-Type
T-Type
12
14.5 ns
8
8.5
ns
9
10
ns
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Clock
tWH
Width
LOW
HIGH
0
0
ns
7.5
10 ns
6
7.5
ns
6
7.5
ns
External Feedback 1/(tS + tCO)
Maximum
fMAX
Frequency
(Note 1) Internal Feedback (fCNT)
D-Type
T-Type
D-Type
T-Type
64
53
MHz
59
50
MHz
80
61.5
MHz
72.5
57
MHz
No Feedback
1/(tS + tH)
80
66.5
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output (Note 3)
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
8
8.5
ns
0
0
ns
8.5
12 ns
6
7.5
ns
14.5
17 ns
tSIR
Input Register Setup Time
tHIR
Input Register Hold Time
tICO
Input Register Clock to Combinatorial Output
tICS
Input Register Clock to Output Register Setup
D-Type
2.5
2.5
ns
3
3
ns
16
18 ns
12
14.5
ns
T-Type
13
16
ns
tWICL
tWICH
Input Register
Clock Width
LOW
HIGH
6
7.5
ns
6
7.5
ns
fMAXIR
Maximum Input Register Frequency 1/(tWICL + tWICH)
80
66.5
MHz
tSIL
Input Latch Setup Time
tHIL
Input Latch Hold Time
tIGO
Input Latch Gate to Combinatorial Output
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
2.5
2.5
ns
3
3
ns
17
20.5 ns
19.5
23 ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
10.5
11
ns
tIGS
Input Latch Gate to Output Latch Setup
13.5
16
ns
MACH210A-12/14 (Ind)
17
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