MACH210-12JI データシートの表示（PDF） - Advanced Micro Devices
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MACH210-12JI Datasheet PDF : 51 Pages
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AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C,
VOUT = 2.0 V f = 1 MHz
Typ Unit
6
pF
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
-12
-15
-20
Min Max Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
12
15
20 ns
Setup Time from Input, I/O,
tS
or Feedback to Clock
D-type 7
10
13
ns
T-type 8
11
14
ns
tH
Register Data Hold Time
tCO
Clock to Output (Note 3)
tWL
Clock
tWH
Width
0
0
0
ns
8
10
12 ns
LOW
6
6
8
ns
HIGH
6
6
8
ns
External Feedback 1/(tS + tCO)
Maximum
fMAX
Frequency
(Note 1) Internal Feedback (fCNT)
D-type
T-type
D-type
T-type
66.7
62.5
83.3
76.9
50
47.6
66.6
62.5
40
MHz
38.5
MHz
50
MHz
47.6
MHz
No Feedback
1/(tWL + tWH)
83.3
83.3
62.5
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
tHL
Latch Data Hold Time
tGO
Gate to Output (Note 3)
tGWL
Gate Width LOW
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
7
10
13
ns
0
0
0
ns
10
11
12 ns
6
6
8
ns
14
17
22 ns
tSIR
Input Register Setup Time
2
2
2
ns
tHIR
Input Register Hold Time
2
2.5
3
ns
tICO
Input Register Clock to Combinatorial Output
15
18
23 ns
tICS
Input Register Clock to Output Register Setup
D-type 12
15
20
ns
T-type 13
16
21
ns
tWICL
tWICH
Input Register
Clock Width
LOW
6
6
8
ns
HIGH
6
6
8
ns
fMAXIR
Maximum Input Register Frequency 1/(tWICL + tWICH)
83.3
83.3
62.5
MHz
tSIL
Input Latch Setup Time
tHIL
Input Latch Hold Time
tIGO
Input Latch Gate to Combinatorial Output
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
2
2
2
ns
2
2.5
3
ns
17
20
25 ns
19
22
27 ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
9
12
15
ns
tIGS
Input Latch Gate to Output Latch Setup
13
16
21
ns
20
MACH210-12/15/20 (Com’l)
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