MACH210-12 データシートの表示（PDF） - Advanced Micro Devices

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MACH210-12

High-Density EE CMOS Programmable Logic

Advanced Micro Devices 

AMD

The I/O Cell

The I/O cell in the MACH210 consists of a three-state

output buffer. The three-state buffer can be configured

in one of three ways: always enabled, always disabled,

or controlled by a product term. If product term control is

chosen, one of two product terms may be used to

provide the control. The two product terms that are

available are common to all I/O cells in a PAL block.

These choices make it possible to use the macrocell as

an output, an input, a bidirectional pin, or a three-state

output for use in driving a bus.

PCI Compliance

The MACH210A-7/10 is fully compliant with the PCI

Local Bus Specification published by the PCI Special

Interest Group. The MACH210A-7/10’s predictable

timing ensures compliance with the PCI AC specifica-

tions independent of the design. On the other hand, in

CPLD and FPGA architectures without predictable

timing, PCI compliance is dependent upon routing and

product term distribution.

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MACH210-7/10/12/15/20, Q-12/15/20

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