MAX15048 データシートの表示（PDF） - Maxim Integrated

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MAX15048

Triple-Output Buck Controllers with Tracking/Sequencing

Maxim Integrated 

MAX15048/MAX15049

Triple-Output Buck Controllers

with Tracking/Sequencing

(fSW) is programmable between 200kHz and 1.2MHz

(see the Setting the Switching Frequency section). The

peak-to-peak inductor current (DIP-P), which reflects

the peak-to-peak output ripple, is worst at the maximum

input voltage. See the Output-Capacitor Selection sec-

tion to verify that the worst-case output current ripple is

acceptable. The inductor saturation current (ISAT) is also

important to avoid runaway current during continuous

output short-circuit conditions. Select an inductor with an

ISAT specification higher than the maximum peak cur-

rent. Inductor parasitic resistance (DCR) causes copper

losses and affects efficiency. Select a low-loss inductor

having the lowest possible DCR that fits in the allocated

dimensions.

Input-Capacitor Selection

The discontinuous input current of the buck converter

causes large input-ripple currents, and therefore, the

input capacitor must be carefully chosen to withstand

the input-ripple current and keep the input-voltage

ripple within design requirements. The 120° ripple phase

operation increases the frequency of the input capacitor

ripple current to thrice the individual converter switching

frequency. When using ripple phasing, the worst-case

input-capacitor ripple current is when only one converter

with the highest output current is on.

The input-voltage ripple comprises DVQ (caused by the

capacitor discharge) and DVESR (caused by the ESR of

the input capacitor). The total voltage ripple is the sum of

DVQ and DVESR, which peaks at the end of the on cycle.

Calculate the input capacitance and ESR required for a

specified ripple using the following equations:

ESR =

∆VESR

ILOAD(MAX)

+

∆IP-P

2





CIN

=

ILOAD(MAX)

×







VOUT_

VIN

(∆VQ + fSW )







where:

( ) ∆IP-P

= VIN

- VOUT_ × VOUT_

VIN × fSW × L

ILOAD(MAX) is the maximum output current, DIP-P is the

peak-to-peak inductor current, and fSW is the switching

frequency.

For the condition with only one converter on, calculate

the input-ripple current using the following equation:

ICIN(RMS) = ILOAD(MAX) × VOUT_ × (VIN - VOUT_ )

VIN

The MAX15048/MAX15049 include UVLO hysteresis to

avoid possible unintentional chattering during turn-on.

Use additional bulk capacitance if the input source

impedance is high. At lower input voltage, additional

input capacitance helps avoid possible undershoot

below the UVLO threshold during transient loading.

Output-Capacitor Selection

The allowed output-voltage ripple and the maximum

deviation of the output voltage during load steps deter-

mine the required output capacitance and its ESR. The

steady-state output ripple is mainly composed of DVQ

(caused by the capacitor discharge) and DVESR (caused

by the voltage drop across the ESR of the output capaci-

tor). The equations for calculating the output capaci-

tance and its ESR are:

COUT =

∆IP-P

8 × ∆VQ × fSW

ESR = ∆VESR

∆IP-P

DVESR and DVQ are not directly additive since they are

out of phase from each other. If using ceramic capaci-

tors, which generally have low ESR, DVQ dominates. If

using electrolytic capacitors, DVESR dominates.

The allowable deviation of the output voltage during fast-

load transients also affects the output capacitance, its

ESR, and its ESL. The output capacitor supplies the load

current during a load step until the controller responds

with a greater duty cycle. The response time (tRESPONSE)

depends on the gain bandwidth of the converter (see the

Compensation Design Guidelines section). The resistive

drop across the output capacitor’s ESR, the drop across

the capacitor’s ESL, and the capacitor discharge causes

a voltage droop during the load-step (ISTEP). Use a com-

bination of low-ESR tantalum/aluminum electrolytic and

ceramic capacitors for better load-transient and voltage-

ripple performance. Nonleaded capacitors and capaci-

tors in parallel help reduce the ESL. Keep the maximum

output-voltage deviation below the tolerable limits of the

electronics being powered.

20  

Maxim Integrated

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