MAX1889 データシートの表示（PDF） - Maxim Integrated

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MAX1889

Triple-Output TFT LCD Power Supply with Fault Protection

Maxim Integrated 

Triple-Output TFT LCD Power Supply

with Fault Protection

Pin Description

PIN

NAME

FUNCTION

Active-Low Shutdown Control Input. Pull SHDN below the 0.4V logic-low level to turn off all sections

1

SHDN of the device and pull the GATE pin high. Pull SHDN above the 1.6V logic-high level to enable the

device. Do not leave SHDN floating.

2

PGND

Power Ground. PGND is the source of the N-channel power MOSFET. Connect PGND to the analog

ground (GND) at the device’s pins.

3

GND Analog Ground. Connect GND to the power ground (PGND) at the device’s pins.

4

REF

Internal Reference Bypass Terminal. Connect a 0.22µF ceramic capacitor from REF to the analog

ground (GND). External load capability is at least 50µA.

Main Step-Up Regulator Feedback Input. FB regulates to 1.25V nominal. Connect FB to the center of

5

FB

a resistive voltage-divider between the main output (VMAIN) and the analog ground (GND) to set the

main step-up regulator output voltage. Place the resistive voltage-divider close to the pin.

Negative Linear-Regulator Feedback Input. FBN regulates to 125mV nominal. Connect FBN to the

6

FBN

center of a resistive voltage-divider between the negative output (VNEG) and the REF to set the

negative linear-regulator output voltage. Place the resistive voltage-divider close to the pin.

Negative Linear-Regulator Base Drive. Open drain of an internal P-channel MOSFET. Connect DRVN

7

DRVN to the base of the external linear-regulator NPN pass transistor (see Pass Transistor Selection

section).

Positive Linear-Regulator Base Drive. Open drain of an internal N-channel MOSFET. Connect DRVP

8

DRVP to the base of the external linear-regulator PNP pass transistor (see Pass Transistor Selection

section).

Positive Linear-Regulator Feedback Input. FBP regulates to 1.25V nominal. Connect FBP to the

9

FBP

center of a resistive voltage-divider between the positive output (VPOS) and the analog ground (GND)

to set the positive linear-regulator output voltage. Place the resistive voltage-divider close to the pin.

Frequency Select Input. Pull FREQ above logic-high level (0.7 × VIN) to set the frequency to 1MHz

10

FREQ and pull FREQ below logic-low level (0.3 × VIN) to set the frequency to 500kHz. Do not leave FREQ

floating.

11

LX

Switching Node. Drain of the internal N-channel power MOSFET for the main step-up regulator.

12

TGND Internal connection. Connect this pin to ground.

Overcurrent Comparator Inverting Input. OCN connects to the center tap of a resistive voltage-

13

OCN divider connected to the drain of the input protection P-channel MOSFET (see the Input Overcurrent

Protection section). If unused, connect OCN to REF.

Overcurrent Comparator Noninverting Input. OCP is connected to the center tap of a resistive

14

OCP

voltage-divider that sets the input overcurrent threshold (see the Input Overcurrent Protection

section). If unused, connect OCP to GND.

15

GATE

Gate Driver Output to the External P-Channel MOSFET (see the Input Overcurrent Protection section).

If unused, leave GATE open.

Supply Input. The supply voltage powers all the control circuitry. The input voltage range is from 2.7V

16

IN

to 5.5V. Bypass with a 0.1µF ceramic capacitor between IN and GND, as close to the pins as

possible.

10 ______________________________________________________________________________________

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