MAX3270(1995) データシートの表示（PDF） - Maxim Integrated

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MAX3270
(Rev.:1995)

155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector

Maxim Integrated 

155Mbps/622Mbps Clock Recovery and

Data Retiming IC with Fully Integrated

Phase/Frequency Detector

__________________Design Procedure

Selecting the Data Rate

The MAX3270 is intended for use in SDH/SONET sys-

tems operating at 155.52Mbps or 622.08Mbps data

rates. TTL inputs (CRS and EXCS) are provided for

selecting the recovered clock rate (Table 1). It is also

possible to switch to an externally supplied clock by

enabling the EXC input. The EXC input is a high-speed

single-ended ECL interface capable of handling serial

clock rates of 155MHz and 622MHz.

Table 1. MAX3270 Logic Table

EXCS

0

0

1

1

CRS

1

0

0

1

RCOP/RCON

155.52Mbps

622.08Mbps

EXC

EXC/4

CRP

38.88Mbps

155.52Mbps

EXC/4

EXC/16

Setting the Loop Filter

The loop filter within the PLL consist of a transconduc-

tance amplifier and the external filter elements Rf and

Cf (Figure 2). The closed-loop bandwidth of a PLL can

be approximated by:

KD KO Gm Rf

where KD is the gain of the phase detector, KO is the

gain of the VCO, and Gm is the transconductance of

the filter amplifier. Because this filter is an integrator, a

zero in the open-loop gain is required for stability. This

zero is set by the following equation:

wz = 1 / (Rf Cf)

where the recommended external values are Rf = 20Ω

and Cf = 2.2µF. To decrease the PLL’s closed-loop

bandwidth, reduce the value of Rf. Decreasing this

bandwidth will improve the MAX3270’s jitter transfer

performance but reduce jitter tolerance. The MAX3270

has been designed (using the recommended values of

Rf and Cf) to meet the Bellcore and CCITT specifica-

tions for jitter tolerance of a Network Element. Carefully

consider the application if a reduction in loop band-

width is desired. By reducing Rf an order of magnitude,

the PLL’s bandwidth becomes more sensitive to the

internal tolerances of the IC. As a result, the loop band-

width may have a wider variation. If Rf is reduced, then

Cf should also be increased to maintain loop stability

and minimize jitter peaking.

MAX3270

F(s)

Gm

FILP FILG FILN

Rf

Rf

F(s) = _G_m__(__w_s__z___+_1_)_

Cf s

Cf

Cf

wz

=

__1__

Rf Cf

Rf = 20Ω

Cf = 2.2µF

Figure 2. Loop Filter

RECOVERED DATA OUTPUT

(213-1 PRBS WITH 200 CONSECUTIVE ONES

BER <10-12, 622Mbps)

200 ONES

PRBS

1.532µs

100ns/div

2.532µs

Figure 3. Recovered Data Output

The MAX3270 is optimally designed to acquire lock

and to provide a bit-error rate (BER) of less than 10-12

for long strings of consecutive zeros or ones. Using the

recommended external values for Rf = 20Ω and Cf =

2.2µF, measured results show that the MAX3270 can

tolerate more than 200 consecutive ones or zeros.

Figure 3 shows a bit stream of 213 - 1 PRBS with 200

consecutive ones.

8 _______________________________________________________________________________________

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