MAX335(1996) データシートの表示（PDF） - Maxim Integrated
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MAX335 Datasheet PDF : 12 Pages
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Serial Controlled, 8-Channel SPST Switch
_____________________Pin Description
PIN NAME
FUNCTION
1
SCLK Serial Clock Input
2
V+
Positive Supply Voltage
3
DIN
Serial Data Input
4
GND Ground
5
NOØ Switch 0
6
COMØ Switch 0
7
NO1 Switch 1
8
COM1 Switch 1
9
NO2 Switch 2
10
COM2 Switch 2
11
NO3 Switch 3
12
COM3 Switch 3
13
COM4 Switch 4
14
NO4 Switch 4
15
COM5 Switch 5
16
NO5 Switch 5
17
COM6 Switch 6
18
NO6 Switch 6
19
COM7 Switch 7
20
NO7 Switch 7
21
V-
Negative Supply Voltage
22
DOUT Serial Data Output
23
VL
Logic Supply/Reset
24
C—S–
Chip Select
______________Detailed Description
Serial Digital Interface
Basic Operation
Refer to Figure 2. The MAX335 interface can be
thought of as an 8-bit shift register controlled by CS.
While CS is low, input data appearing at DIN is clocked
into the shift register synchronous with SCLK’s rising
edge. The data is an 8-bit word, each bit controlling
one of eight switches in the MAX335 (Table 1). DOUT is
the output of the shift register, with data appearing syn-
chronous with SCLK’s falling edge. Data at DOUT is
simply the input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and
out of the shift register. While shifting data, the switches
remain in their original configuration. When the 8 bits of
data have been shifted in, CS is brought high. This
updates the new switch configuration and inhibits fur-
ther data from entering the shift register. Transitions at
DIN and SCLK have no effect when CS is high, and
DOUT holds the last bit in the shift register.
The MAX335 three-wire serial interface is compatible
with the SPI™ and Microwire™ standards. If interfacing
with a Motorola processor serial interface, set CPOL = 0.
The MAX335 is considered a slave device (Figures 2
and 3). Upon power-up, the shift register contains all
zeros, and all switches are off.
The latch that drives the analog switch is only
updated on the rising edge of CS when SCLK is low.
If SCLK is high when CS rises, the latch will not be
updated until SCLK goes low. The CPOL = 1, CPHA = 1
SPI configuration does not update the latch correctly.
Daisy Chaining
For a simple interface using several MAX335s, “daisy
chain” the shift registers as shown in Figure 5. The CS
pins of all devices are connected together, and a
stream of data is shifted through the MAX335s in
series. When CS is brought high, all switches are
updated simultaneously. Additional shift registers may
be included anywhere in series with the MAX335 data
chain.
Addressable Serial Interface
When several serial devices are configured as slaves,
addressable by the processor, DIN pins of each
MAX335 are connected together (Figure 6). Address
decode logic individually controls CS of each slave
device. When a slave is selected, its CS is brought low,
data is shifted in, and CS is brought high to latch the
data. Typically, only one slave is addressed at a time.
DOUT is not used.
Digital Feedthrough
Digital feedthrough energy measures 100nV-sec, which
means that with no filtering at the signal channel,
feedthrough from a sharply rising clock edge into an
unfiltered switch channel can be measured at 1Vp-p for
100ns. However, even 100pF capacitance in the switch
channel, when combined with the switch resistance,
yields a filter that reduces this transient to 10mVp-p
typical. To reduce digital feedthrough, hysteresis
(150mV typ) was added to the SCLK input so triangle
or sine waves may be used.
6 _______________________________________________________________________________________
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