MAX3832 データシートの表示（PDF） - Maxim Integrated

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MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator

Maxim Integrated 

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

PIN

1, 16, 25, 28,

29, 32, 43, 48,

49, 60, 63

2, 5, 10, 13,

17, 24, 38, 55,

59, 64

3

4

6

NAME

GND

VCC

SDO-

SDO+

LBEN

7

TEST

8

9

11

12

14

15

18–23, 26, 27

SDI+

SDI-

SCLKI+

SCLKI-

PCLKO-

PCLKO+

N.C.

30

RSETFR

31

LOF

33

TRIEN

34, 36, 39, 41

35, 37, 40, 42

44, 46, 50, 52

45, 47, 51, 53

PDO4- to PDO1-

PDO4+ to PDO1+

PDI4- to PDI1-

PDI4+ to PDI1+

54

PLBEN

56

RCLKI-

57

RCLKI+

Supply Ground

FUNCTION

Pin Description

+3.3V Supply Voltage

Negative CML Serial-Data Output, 2.488Gbps

Positive CML Serial-Data Output, 2.488Gbps

Line Loopback Enable. When this TTL input is forced low, the CML serial-data inputs (SDI±)

route directly to the CML serial-data outputs (SDO±). No other inputs or outputs are affected.

An internal 15kΩ pull-up resistor pulls LBEN high for normal operation. See Test Loopbacks.

Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates

a standard OC-12 SONET-like frame of 12 A1s, 12 A2s, and 9696 bytes of 27 - 1 pseudo-

random bits. This also enables an internal serial-system-loopback path. The CML inputs

(SDI± and the SCLK±) and the LVDS inputs are ignored in this mode. An internal 15kΩ pull-

up resistor pulls TEST high for normal operation.

Positive CML Serial-Data Input, 2.488Gbps

Negative CML Serial-Data Input, 2.488Gbps

Positive CML Serial-Clock Input, 2.488GHz

Negative CML Serial-Clock Input, 2.488GHz

Negative LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)

Positive LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)

No Connection

Frame Reset. When this TTL input is forced low, the frame detector and pattern generator

are reset. The LOF output is also asserted low. An internal 15kΩ pull-up resistor pulls

RSETFR high for normal operation.

TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition.

3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a high-

impedance state. An internal 15kΩ pull-up resistor pulls TRIEN high for normal operation.

Negative LVDS Parallel-Data Output, 622Mbps

Positive LVDS Parallel-Data Output, 622Mbps

Negative LVDS Parallel-Data Input, 622Mbps

Positive LVDS Parallel-Data Input, 622Mbps

Parallel System Loopback Enable. When this TTL input is forced low, the LVDS parallel

inputs route through the elastic store to the LVDS parallel outputs. This bypasses the high-

speed mux and demux. An internal 15kΩ pull-up resistor pulls PLBEN high for normal oper-

ation.

Negative LVDS Reference Clock Input, 155.52MHz

Positive LVDS Reference Clock Input, 155.52MHz

6 _______________________________________________________________________________________

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