MAX3815 データシートの表示（PDF） - Maxim Integrated
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MAX3815 Datasheet PDF : 11 Pages
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TMDS Digital Video Equalizer for DVI/HDMI
Cables
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, unless
otherwise noted.)
EQCONTROL VOLTAGE (RELATIVE TO VCC)
vs. CABLE LENGTH (MANUAL EQ CONTROL)
0
CABLE IS TENSOLITE TWIN-AX
-0.1 28 AWG WITH APPROXIMATELY
200 MAX3815 toc13
180
-0.2 0.34dB OF LOSS PER FOOT AT
160
825MHz
-0.3
140
-0.4
EQCONTROL VOLTAGE
120
-0.5
100
-0.6
80
-0.7
60
-0.8
RESIDUAL JITTER 40
AT 1.65Gbps
-0.9
20
-1.0
0
0
20 40 60 80 100 120
CABLE LENGTH (ft)
EQUALIZER OUTPUT EYE AFTER 120ft
OF CABLE (DATA RATE = 1.65Gbps)
MAX3815 toc14
CABLE IS TENSOLITE
TWIN-AX 28 AWG
200mV/div
100ps/div
LOSS-OF-CLOCK ASSERT THRESHOLD
vs. CABLE LENGTH
350
CABLE IS TENSOLITE TWIN-AX 28 AWG
300
250
200
165MHz CLOCK FREQUENCY
150
100
50
0
0
25MHz CLOCK FREQUENCY
20 40 60 80 100 120
CABLE LENGTH (ft)
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8, 9,
12, 13, 16,
38, 41, 43, 44
2
3
6
7
10
11
14
15
VCC
RX0_IN-
RX0_IN+
RX1_IN-
RX1_IN+
RX2_IN-
RX2_IN+
RXC_IN+
RXC_IN-
Supply Voltage. All pins must be connected to VCC.
Negative Data Input, CML
Positive Data Input, CML
Negative Data Input, CML
Positive Data Input, CML
Negative Data Input, CML
Positive Data Input, CML
Positive Clock Input, CML
Negative Clock Input, CML
Equalizer Control. This pin allows the user to control the equalization level of the MAX3815. Connect
17
EQCONTROL
the pin to GND for automatic operation. Set the voltage to VCC / 2 for minimum equalization, or set
the voltage between VCC - 1V to VCC for manual equalization. See the Typical Operating
Characteristics for more information.
18
CLKLOS
Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS
clock from the cable.
19
PWRDWN Power-Down Input, LVTTL. This input allows the IC to be powered down to conserve power. Connect
high for normal operation. Pull low for power-down mode.
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