+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Interfacing with PECL Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
50Ω termination (Figure 7). AC-coupling is also
required to maintain the input common-mode level.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled impedance transmission lines to inter-
face with the MAX3880 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
VCC as possible. To reduce feedthrough, take care to
isolate the input signals from the output signals.
VCC
0.1µF 25Ω
SDI+
PECL
LEVELS
0.1µF
100Ω
25Ω
SDI-
50Ω 50Ω
Chip Information
TRANSISTOR COUNT: 4102
MAX3880
Figure 7. Interfacing with PECL Input Levels
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