MAX394(1995) データシートの表示（PDF） - Maxim Integrated

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MAX394
(Rev.:1995)

Low-Voltage, Quad, SPDT, CMOS Analog Switch

Maxim Integrated 

Low-Voltage, Quad, SPDT,

CMOS Analog Switch

______________________________________________Test Circuits/Timing Diagrams

3V

VIN

0V

tR < 20ns

tF < 20ns

50%

+10V

VCOM 0V

-10V

tOFF

tOFF

tOPEN

50%

50%

tON

Figure 2. Switching-Time Test Circuit

C

+5V

50%

tON

50%

50%

tOPEN

+10V

-10V

IN_

NC_

SWITCH OUTPUT

COM_

NO_

300Ω

MAX394

LOGIC

INPUT

V+

GND

V-

+15V

-15V

(REPEAT TEST FOR IN2, IN3, AND IN4.)

C

+5V

CAPACITANCE

METER

V+

COM

MAX394

IN

NC

or NO

GND

V-

0V or 2.4V

C

CAPACITANCE

METER

V+

COM MAX394

IN

NC or

NO

GND

V-

0V or 2.4V

C

-5V

Figure 3. Channel Off Capacitance

-5V

Figure 4. Channel On Capacitance

LOGIC +3V

INPUT

50%

0V

VCOM

VO1

0.9VO

SWITCH 0V

OUTPUT VCOM

VO2

0.9VO

SWITCH 0V

OUTPUT

tD

tD

Figure 5. Break-Before-Make Delay

+5V

LOGIC

INPUT

V+

NO

VCOM COM_

NC

IN_ MAX394

GND

V-

VO2 RL1

RL2

CL2

VO1

CL1

-5V

RL = 1kΩ

CL = 35pF

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

LOGIC 0 INPUT.

10 ______________________________________________________________________________________

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