MAX3940E データシートの表示（PDF） - Maxim Integrated

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MAX3940E

10Gbps EAM Driver with Integrated Bias Network

Maxim Integrated 

10Gbps EAM Driver with Integrated

Bias Network

PAD

BP1, BP2,

BP4, BP5,

BP7–BP12,

BP14, BP15,

BP17–BP24,

BP26, BP27,

BP28

BP3

BP6

BP13

BP16

BP25

BP29

BP30

BP31

BP32

BP33–BP41

BP42

BP43

BP44

NAME

FUNCTION

Pad Description

GND Ground. All pads must be connected to board ground.

DATA+ Noninverting Data Input, with 50Ω On-Chip Termination

DATA- Inverting Data Input, with 50Ω On-Chip Termination

CLK+ Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination

CLK- Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination

OUT Driver Output. Provides both modulation and bias output. DC-couple to EAM.

MODEN

RTEN

BIASSET

TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM

in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to VEE.

Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch.

Bias Current Set. Apply a voltage to set the bias current of the driver output.

MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.

VEE

Negative Supply Voltage. All pads must be connected to VEE.

PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).

PWC-

PLRT

Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width

adjustment feature (see the Design Procedure section).

Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the

differential signal polarity. Contains an internal 100kΩ pullup to GND.

Detailed Description

The MAX3940 EAM driver consists of two main parts: a

high-speed modulation driver and an EAM-biasing

block. The clock and data inputs to the driver are com-

patible with PECL and CML logic levels. The modula-

tion and bias current are output through the OUT pad.

The modulation output stage is composed of a high-

speed differential pair and a programmable current

source with a maximum modulation current of 120mA.

The rise and fall times are typically 23ps. The modulation

current is designed to produce an EAM voltage up to

3.0VP-P when driving a 50Ω module. The 3.0VP-P results

from 120mAP-P through the parallel combination of the

50Ω EAM load and the internal 50Ω back termination.

Polarity Switch

The MAX3940 includes a polarity switch. When the

PLRT pad is high or left floating, the output maintains

the polarity of the input data. When the PLRT pad is

low, the output is inverted relative to the input data.

Clock/Data Input Logic Levels

The MAX3940 is directly compatible with ground-refer-

ence CML. Either DC- or AC-coupling may be used for

CML referenced to ground. For all other logic types,

AC-coupling should be used.

Optional Data Input Latch

To reject pattern-dependent jitter in the input data, a syn-

chronous differential clock signal should be connected to

the CLK+ and CLK- inputs, and the RTEN control input

should be connected to VEE.

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