MAX5019 データシートの表示（PDF） - Maxim Integrated

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MAX5019

Current-Mode PWM Controllers with Integrated Startup Circuit

Maxim Integrated 

Current-Mode PWM Controllers with Integrated

Startup Circuit

VIN

(36V TO 72V)

CDD

4.7µF

CCC

10µF

CSS

0.1µF

Figure 2. Forward Converter

1N4148

6 NT

VDD

MAX5020

VCC

14 NR

CMHD2003

CIN

V+

3✕

0.47µF NP

14

NDRV

M1

IRF640N

SBL204OCT

L1

4.7µH

NS 20Ω

5

1nF

SS_SHDN

CS

100Ω

RSENSE

100mΩ

GND

FB

CFB

(OPTIONAL)

VOUT

5V/10A

COUT

3✕

560µF

0.1µF

R1

2kΩ

R2

2kΩ

vantage to this is that the MOSFET voltage rating must

be higher and that slope compensation must be provid-

ed to stabilize the inner current loop. The MAX5019

provides internal slope compensation.

Internal Regulators

The internal regulators of the MAX5019/MAX5020

enable initial startup without a lossy startup resistor and

regulate the voltage at the output of a tertiary (bias)

winding to provide power for the IC. At startup V+ is

regulated down to VCC to provide bias for the device.

The VDD regulator then regulates from the output of the

tertiary winding to VCC. This architecture allows the ter-

tiary winding to only have a small filter capacitor at its

output thus eliminating the additional cost of a filter

inductor.

When designing the tertiary winding calculate the num-

ber of turns so the minimum reflected voltage is always

higher than 12.7V. The maximum reflected voltage

must be less than 36V.

To reduce power dissipation the high-voltage regulator

is disabled when the VDD voltage reaches 12.7V. This

greatly reduces power dissipation and improves effi-

ciency. If VCC falls below the undervoltage lockout

threshold (VCC = 6.6V), the low-voltage regulator is dis-

abled, and soft-start is reinitiated. In undervoltage lock-

out the MOSFET driver output (NDRV) is held low.

If the input voltage range is between 13V and 36V, V+

and VDD may be connected to the line voltage provid-

ed that the maximum power dissipation is not exceed-

ed. This eliminates the need for a tertiary winding.

Undervoltage Lockout (UVLO), Soft-Start,

and Shutdown

The soft-start feature of the MAX5019/MAX5020 allows

the load voltage to ramp up in a controlled manner,

thus eliminating output voltage overshoot.

While the part is in UVLO, the capacitor connected to

the SS_SHDN pin is discharged. Upon coming out of

UVLO an internal current source starts charging the

capacitor to initiate the soft-start cycle. Use the follow-

ing equation to calculate total soft-start time:

tstartup

=

0.45

ms

nF

×

Css

where CSS is the soft-start capacitor as shown in Figure 2.

Operation begins when VSS_SHDN ramps above 0.6V.

When soft-start has completed, VSS_SHDN is regulated

8 _______________________________________________________________________________________

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