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MAX5073 データシートの表示(PDF) - Maxim Integrated

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MAX5073 Datasheet PDF : 25 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V
SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms
SGND to PGND .....................................................-0.3V to +0.3V
VL, BYPASS to SGND Short Circuit............................Continuous
VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)
Continuous Power Dissipation (TA = +70°C)
BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD2, PGOOD1 to
28-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*
SGND .................................................................-0.3V to +30V
Package Junction-to-Case Thermal Resistance (θJC).......2°C/W
BST1/VDD1 to SOURCE1,
Operating Temperature Ranges:
BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V
MAX5073ETI (TMIN to TMAX)............................-40°C to +85°C
SOURCE_ to SGND................................................-0.6V to +25V
MAX5073ATI (TMIN to TMAX) .........................-40°C to +125°C
EN_ to SGND .............................................-0.3V to (VL to +0.3V)
Junction Temperature ......................................................+150°C
CLKOUT, BYPASS, OSC, COMP1,
Storage Temperature Range .............................-65°C to +150°C
COMP2, SYNC, FB_ to SGND ..................-0.3V to (VL + 0.3V)
Lead Temperature (soldering, 10s) .................................+300°C
SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceram-
ic), ROSC = 10k(circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYSTEM SPECIFICATIONS
Input Voltage Range
SYMBOL
(Note 2)
V+
VL = V+
CONDITIONS
MIN TYP MAX UNITS
5.5
23.0
V
4.5
5.5
Operating Supply Current
IQ
VL unloaded, no switching, VFB_ = 1V, V+ =
12V, ROSC = 60k
2.2
4
mA
V+ Standby Supply Current
Efficiency
STARTUP/VL REGULATOR
VL Undervoltage Lockout Trip
Level
VL Undervoltage Lockout
Hysteresis
VL Output Voltage
BYPASS OUTPUT
BYPASS Voltage
BYPASS Load Regulation
SOFT-START
Digital Ramp Period
Soft-Start Steps
ISTBY
η
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60k(MAX5073ETI)
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60k(MAX5073ATI)
VOUT1 = 3.3V at 1.5A,
VOUT2 = 2.5V at 0.75A
(fSW = 1.25MHz)
V+ = VL = 5V
V+ = 12V
V+ = 16V
0.6
1.2
mA
0.6
1.4
82
80
%
78
UVLO VL falling
3.95
4.1
4.25
V
VL
V+ = 5.5V to 23V, ISOURCE = 0 to 40mA
175
mV
4.9
5.2
5.5
V
VBYPASS
IBYPASS = 0, ROSC = 60k(MAX5073ETI)
IBYPASS = 0, ROSC = 60k(MAX5073ATI)
1.98
1.975
2.00
2.00
2.02
2.025
V
VBYPASS 0 IBYPASS 50µA, ROSC = 60k
0
2
10
mV
Internal 6-bit DAC
2048
64
fOSC
clock
cycles
steps
2 _______________________________________________________________________________________

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