MAX5362(2001) データシートの表示（PDF） - Maxim Integrated

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MAX5362
(Rev.:2001)

Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package

Maxim Integrated 

Low-Cost, Low-Power 6-Bit DACs with

2-Wire Serial Interface in SOT23 Package

TIMING CHARACTERISTICS (continued)

(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMAX to

TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Setup Time for a Repeated

START Condition

tSU, STA

0.6

µs

Data Hold Time

Data Setup Time

Rise Time of Both SDA and

SCL Signals

tHD, DAT

tSU, DAT

tr

0

0.9

µs

100

ns

300

ns

Fall Time of Both SDA and

SCL Signals

tf

300

ns

Setup Time for STOP Condition

Capacitive Load for Each

Bus Line

tSU, STO

Cb

0.6

µs

400

pF

Note 1: Guaranteed from code 1 to code 63.

Note 2: The offset value extrapolated from the range over which the INL is guaranteed.

Note 3: MAX5362, tested at VDD = 5V ±10%.

Note 4: MAX5360, tested at VDD = 3V ±10%; MAX5361, tested at VDD = 5V ±10%.

Note 5: Actual output voltage at full scale is 63/64 ✕ VREF.

Note 6: Output settling time is measured by taking the code from code 1 to code 63, and from code 63 to code 1.

Note 7: Guaranteed by design.

Typical Operating Characteristics

(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA = +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY vs. CODE

0.030

0.025

0.020

0.015

0.010

0.005

0

-0.005

-0.010

-0.015

-0.020

-0.025

-0.030

-0.035

-0.040

-0.045

0

25

50

75

CODE

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0

INTEGRAL NONLINEARITY

vs. TEMPERATURE

0

-0.025

-0.025

-0.050

2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

-0.050

-40 -20 0 20 40 60 80 100

TEMPERATURE (°C)

4 _______________________________________________________________________________________

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