MAX5322 データシートの表示（PDF） - Maxim Integrated
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MAX5322 Datasheet PDF : 18 Pages
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±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
TIMING CHARACTERISTICS
(VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND_ = 0, VREF_ = 5V, RLOAD = 2kΩ, ,CLOAD = 250pF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Frequency
SCLK Clock Period
tCP
SCLK Pulse-Width High
tCH
For nondaisy-chain use
SCLK Pulse-Width Low
For nondaisy-chain use
tCL
For daisy-chain use
CS Fall to SCLK Rise Setup Time
tCSS
SCLK Rise to CS Rise Hold Time
tCSH
+2.7V ≤ VCC ≤ +3.6V
+4.5V ≤ VCC ≤ +5.5V
DIN Setup Time
tDS
DIN Hold Time
tDH
LDAC Pulse Width
tLD
CS Rise to LDAC Low Setup Time
tLDS
+2.7V ≤ VCC ≤ +3.6V
+4.5V ≤ VCC ≤ +5.5V
SCLK Fall to DOUT Valid
Propagation Delay
SCLK Rise to CS Fall Delay
CS Low to DOUT Valid Time
CS High to DOUT Disabled Time
CS Rise to SCLK Rise Hold Time
tDO1
tCS0
tCSE
tCSD
tCS1
CLOAD = 20pF, +2.7V ≤ VCC ≤ +3.6V
CLOAD = 20pF, +4.5V ≤ VCC ≤ +5.5V
CLOAD = 20pF
CS Pulse-Width High
CLR Pulse-Width Low
tCSW
tCLR
+2.7V ≤ VCC ≤ +3.6V
+4.5V ≤ VCC ≤ +5.5V
Note 1: Output unloaded, digital inputs = VCC or DGND.
Note 2: ∆VDD = 15.5V to 14.5V, ∆VSS = -15.5V to -14.5V, input code = 14hex to FFFhex
Note 3: Accuracy is guaranteed from code 14hex to FFFhex
10
MHz
100
ns
45
ns
45
ns
98
40
ns
15
ns
10
20
ns
10
ns
50
ns
100
ns
50
100
ns
80
10
ns
120
ns
120
ns
50
ns
200
ns
100
50
ns
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