MAX5424ETA データシートの表示（PDF） - Maxim Integrated
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MAX5424ETA Datasheet PDF : 11 Pages
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256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
(CS), data clock (SCLK), and data in (DIN). Drive CS
low to enable the serial interface and clock data syn-
chronously into the shift register on each SCLK rising
edge.
The WRITE commands (C1, C0 = 00 or 01) require 16
clock cycles to clock in the command and data (Figure
2a). The COPY commands (C1, C0 = 10, 11) can use
either eight clock cycles to transfer the command bits
(Figure 2b) or 16 clock cycles with 8 data bits that are
disregarded by the device (Figure 2a).
Table 1. Register Map
CLOCK EDGE
123456
Bit name
Write wiper register
Write NV register
— — C1 C0 — —
000000
000100
Copy wiper register to NV
register
0
0
1
0
0
0
Copy NV register to wiper
register
0
0
1
1
0
0
After loading data into the shift register, drive CS high
to latch the data into the appropriate potentiometer
control register and disable the serial interface. Keep
CS low during the entire serial-data stream to avoid
corruption of the data.
The serial-data timing for the potentiometer is shown in
Figures 1 and 2.
7 8 9 10 11 12 13 14 15 16
— — D7 D6 D5 D4 D3 D2 D1 D0
0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 ————————
0 0 ————————
A) 16-BIT COMMAND/DATA WORD
CS
SCLK
DIN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
B) 8-BIT COMMAND WORD
CS
SCLK
1
2
3
4
5
6
7
8
DIN
Figure 2. Digital-Interface Format
C1 C0
8 _______________________________________________________________________________________
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