MAX7034(2008) データシートの表示（PDF） - Maxim Integrated
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MAX7034 Datasheet PDF : 13 Pages
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PIN
1
2, 7
3
4
5, 10
6
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
315MHz/434MHz ASK Superheterodyne
Receiver
Pin Description
NAME
XTAL1
AVDD
LNAIN
LNASRC
AGND
LNAOUT
MIXIN1
MIXIN2
IRSEL
MIXOUT
DGND
DVDD
EN_REG
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
VDD5
DATAOUT
PDOUT
SHDN
XTAL2
Crystal Input 1
FUNCTION
Positive Analog Supply Voltage. AVDD is connected to an on-chip +3.4V low-dropout regulator. Both
AVDD pins must be externally connected to each other. Bypass pin 2 to AGND with a 0.1µF capacitor as
close as possible to the pin (see the Typical Application Circuit). Bypass pin 7 with a 0.01µF capacitor.
Low-Noise Amplifier Input. See the Low-Noise Amplifier section.
Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
Analog Ground
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
2nd Differential Mixer Input. Connect to AVDD side of the LC tank filter through a 100pF capacitor.
See the Typical Application Circuit.
Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at
434MHz. See the Mixer section.
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01µF capacitor as close
as possible to the pin.
Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device
operation between +3.0V and +3.6V. See the Voltage Regulator section.
Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to
select divider ratio of 32.
1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5.0V Supply Voltage
Digital Baseband Data Output
Peak-Detector Output
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100kΩ resistor.
Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section.
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