MAX7034 データシートの表示（PDF） - Maxim Integrated

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MAX7034

315MHz/434MHz ASK Superheterodyne Receive

Maxim Integrated 

MAX7034

315MHz/434MHz ASK Superheterodyne

Receiver

Pin Description (continued)

PIN

4

5, 10

6

8

9

NAME

LNASRC

AGND

LNAOUT

MIXIN1

MIXIN2

FUNCTION

Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set

LNA input impedance. See the Low-Noise Amplifier section.

Analog Ground

Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise

Amplifier section.

1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See

the Typical Application Circuit.

2nd Differential Mixer Input. Connect to VDD3 side of the LC tank filter through a 100pF capacitor. See

the Typical Application Circuit.

Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL

11

IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at

434MHz. See the Mixer section.

12

MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.

13

DGND Digital Ground

14

DVDD

Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF

capacitor as close as possible to the pin (see the Typical Application Circuit).

15

EN_REG

Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device

operation between +3.0V and +3.6V. See the Voltage Regulator section.

16

XTALSEL

Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high

to select fLO/fXTAL ratio of 32.

17

IFIN1

1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz

bandpass filter.

18

IFIN2

2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF

capacitor as close as possible to the pin.

19

DFO

Data Filter Output

20

DSN

Negative Data Slicer Input

21

OPP

Noninverting Op-Amp Input for the Sallen-Key Data Filter

22

DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.

23

DSP

Positive Data Slicer Input

+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For +5V

24

VDD5

operation, VDD5 is the input to an on-chip voltage regulator whose +3.4V output appears at AVDD pin

2. (see the Voltage Regulator section and the Typical Application Circuit).

25

DATAOUT Digital Baseband Data Output

26

PDOUT Peak-Detector Output

27

SHDN

Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a

100kΩ resistor.

28

XTAL2 Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section.

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