MAX7060(2010) データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX7060 Datasheet PDF : 30 Pages
| |||
280MHz to 450MHz Programmable
ASK/FSK Transmitter
AC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = VAVDD =
VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless oth-
erwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for
optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design
and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Maximum Carrier Harmonics
(Note 1)
-24
dBc
Reference Spur
PAOUT Capacitor Tuning Range
-43
dBc
0 to 7.75
pF
SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS
(SPI timing characteristics are valid for both 3V and 5V modes. SPI timing is production tested at worst-case temperature and supply
with a clock frequency of 3MHz.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Minimum SCLK_PWR0 Low to
Falling-Edge of CS_DEV Setup Time
tSC
30
ns
Minimum CS_DEV Low to Rising
Edge of SCLK_PWR0 Setup Time
tCSS
15
ns
Minimum SCLK_PWR0 Low to
Rising Edge of CS_DEV Setup
Time
tHCS
60
ns
Minimum SCLK_PWR0 Low After
Rising Edge of CS_DEV Hold Time
tHS
15
ns
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Setup Time
tDS
30
ns
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Hold Time
tDH
15
ns
Minimum SCLK_PWR0 High Pulse
Width
tCH
120
ns
Minimum SCLK_PWR0 Low Pulse
Width
Minimum CS_DEV High Pulse
Width
Maximum Transition Time from
Falling-Edge of CS_DEV to Valid
GPO2_MOD
Maximum Transition Time from
Falling Edge of SCLK_PWR0 to
Valid GPO2_MOD
tCL
tCSH
tCSG
tCG
CL = 10pF load capacitance from
GPO2_MOD to DGND
CL = 10pF load capacitance from
GPO2_MOD to DGND
120
ns
120
ns
400
ns
400
ns
Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match.
Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded).
Note 3: Dependent on PCB trace capacitance.
_______________________________________________________________________________________ 7
Share Link: 