M7010R データシートの表示（PDF） - STMicroelectronics

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M7010R

16K x 68-bit Entry NETWORK SEARCH ENGINE

STMicroelectronics 

M7010R

The NFA Register

Bit [0] of each 68-bit data entry is a special bit des-

ignated for use in the operation of the LEARN

command. In 68-bit configurations, the Bit[0] indi-

cates whether a location is full (bit set to '1') or

empty (bit set to '0'). Every WRITE/LEARN com-

mand loads the address of first 68-bit location that

contains a “0” in the entry’s Bit[0]. This is stored in

the NFA register. If all the bits in a device are set

to '1,' the M7010R asserts FULO[1:0] to '1.'

In a 136-bit configuration, the LSB of this register

is always set to '0.' The host ASIC must set Bit 0

and Bit 68 in a 136-bit word to either '0' or '1' to in-

dicate full/empty status for a 136-bit entry.

Note: Both Bits 0 and Bit 68 must be set to '0' or

'1' (e.g., '10' or '01' settings are invalid).

Table 14. NFA Register

Address

67 - 14

60

Reserved

13 - 0

Index

SEARCH ENGINE ARCHITECTURE

The M7010R consists of 16k x 68-bit storage cells

referred to as “data bits.” There is a mask cell cor-

responding to each data cell. Figure 17 shows the

three organizations of the device based on the val-

ue of CFG bits in the COMMAND register.

During a SEARCH operation, the SEARCH Data

Bit (S), Data Array Bit (D), Mask Array Bit (M) and

the Global Mask Bit (G) are used in the following

manner to generate a match at that bit position

(see Table 15, page 25).

The entry with all matched bit positions results in a

successful search in the M7010R. In order for a

successful SEARCH to make the device the local

winner in the SEARCH operation, all 68-bit posi-

tions within a device must generate a match for a

68-bit entry in 68-bit-configured quadrants, or all

136-bit positions must generate a match for two

consecutive even and odd 68-bit entries in quad-

rants configured as 136 bits, or all 272-bit posi-

tions must generate a match for four consecutive

entries aligned to four entry-page boundaries of

68-bit entries in quadrants configured as 272 bits.

An arbitration mechanism using a cascade bus de-

termines the global winning device among the lo-

cal winning devices in a SEARCH cycle. The

global winning device drives the SRAM bus, SSV,

and The SSF signals. In the case of a SEARCH

failure, the device(s) with LDEV and LRAM bits set

drive the SRAM bus, SSF, and SSV signals.

The M7010R may be partitioned into up to four (4)

quadrants of different widths (e.g., 34, 68, 136, or

272 bits), even within the same chip (see Applica-

tion Notes AN1338 and AN1339). Figure 18 shows

a sample configuration of different widths.

Data and Mask Addressing

Figure 19, page 26 shows the M7010R data array

and mask array addressing procedure. The data

array and mask array addresses differ only in one

bit in the address cycle of the READ and WRITE

commands.

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