M7010R データシートの表示（PDF） - STMicroelectronics

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M7010R

16K x 68-bit Entry NETWORK SEARCH ENGINE

STMicroelectronics 

M7010R

WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Single Location WRITE Cycle Timing (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . 32

(Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 22.) . . . . . . . . . . . . . 33

WRITE Address Format for Internal Registers (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

WRITE Address Format for Data and Mask Array (Burst WRITE) (Table 24.) . . . . . . . . . . . . . . . . 33

SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

68-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Hardware Diagram for a Table with a Single Device (68-bit Operation) (Figure 24.) . . . . . . . . . . . 34

68-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 25.). . . . . . . . . . . . . . . . . . . 35

Right-Shift of 68-bit Signals for TLSZ Values (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Shift of SSF and SSV from SADR (for different HLAT Values) (Table 26.) . . . . . . . . . . . . . . . . . . . 36

Latency of SEARCH from Instruction to SRAM Access Cycle (68-bit Mode) (Table 27.) . . . . . . . . 36

68-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

x68 Table with One Device (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

136-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Hardware Diagram for a Table with One Device (136-bit Operation) (Figure 27.) . . . . . . . . . . . . . 38

136-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 28.). . . . . . . . . . . . . . . . . . 39

Right-Shift of 136-bit Signals for TLSZ Values (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Shift of SSF and SSV from SADR (for different HLAT values) (Table 29.) . . . . . . . . . . . . . . . . . . . 40

Latency of SEARCH from Instruction to SRAM Access Cycle (136-bit Mode) (Table 30.) . . . . . . . 40

136-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

x136 Table with One Device (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

272-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Diagram for a Table with One Device (272-bit Operation) (Figure 30.) . . . . . . . . . . . . . 42

272-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 31.). . . . . . . . . . . . . . . . . . 43

Right-Shift of 272-bit Signals for TLSZ Values (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Shift of SSF and SSV from SADR (for different HLAT Values) (Table 32.) . . . . . . . . . . . . . . . . . . . 44

Latency of SEARCH from Instruction to SRAM Access Cycle (272-bit Mode) (Table 33.) . . . . . . . 44

272-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

x272 Table with One Device (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Mixed-sized Searches on Tables Configured with Different Width Using an M7010R Device 46

Multiwidth Configuration Example (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Timing Diagram for Mixed SEARCH (One Device) (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

LRAM and LDEV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LEARN Command Timing Diagram (TLSZ = 00) (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LEARN Timing Diagram (TLSZ = 1, except on Last Device) (Figure 36.) . . . . . . . . . . . . . . . . . . . . 50

LEARN Timing Diagram on Device Number 7 (TLSZ = 01) (Figure 37.). . . . . . . . . . . . . . . . . . . . . 51

SRAM WRITE Cycle Latency from Second Cycle of LEARN Instruction (Table 34.) . . . . . . . . . . . 51

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