M7010R
Table 2. Signal Names
Symbol Type
Connection Name
Clocks and Reset
LHI[6:0]
CLK2X
I Master Clock
LHO[1:0]
PHS_L
I Phase
BHI[2:0]
RST_L
I Reset
BHO[2:0]
Command and DQ Bus
FULI[6:0]
CMD[8:0]
I Command Bus
FULO[1:0]
CMDV
I Command Valid
FULL
DQ[67:0]
I/O Address/Data Bus
ACK(1)
T READ Acknowledge
ID[4:0]
EOT(1)
SSF
SSV
T End of Transfer
T SEARCH Successful Flag
T SEARCH Successful Flag Valid
TDI
TCK
SADR[21:0] T SRAM Address
TDO
CE_L
WE_L
OE_L
T SRAM Chip Enable
T SRAM WRITE Enable
T SRAM Output Enable
TMS
TRST_L
ALE_L
T Address Latch Enable
Note: Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate
1. ACK and EOT Signals require a pull-down resistor of 47 ohms.
Cascade Interface
I Local Hit In
O Local Hit Out
I Block Hit In
O Block Hit Out
I Full In
O Full Out
O Full Flag
Device Identification
I Device Identification
Test Access Port
I Test Access Port’s Test Data In
I Test Access Port’s Test Clock
T
Test Access Port’s Test Data
Out
I
Test Access Port’s Test Mode
Select
I Test Access Port’s Reset
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