MAX9236EUM データシートの表示（PDF） - Maxim Integrated

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MAX9236EUM

Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

Maxim Integrated 

MAX9234/MAX9236/MAX9238

Hot-Swappable, 21-Bit, DC-Balanced LVDS

Deserializers

PWRDWN

0.8V

RxCLK IN

RxOUT_

RxCLK OUT

RPDD

HIGH-Z

Figure 8. Power-Down Delay

MAX9234/MAX9236/MAX9238 vs.

MAX9210/MAX9220/MAX9222

The MAX9234/MAX9236/MAX9238 operate in DC-bal-

ance mode only. Pinouts are the same as the

MAX9210/MAX9220/MAX9222 except that pin 6 on the

MAX9234/MAX9236/MAX9238 is no connect (N.C.). DC

balance allows AC-coupling with series capacitors. The

MAX9234/MAX9236/MAX9238 are hot-swappable and

the input frequency can be changed on the fly, but oth-

erwise the specifications and functionality are the same

as the MAX9210/MAX9220/MAX9222 operating in DC-

balance mode. See Table 1.

Applications Information

Selection of AC-Coupling Capacitors

Voltage droop and the DSV of transmitted symbols

cause signal transitions to start from different voltage

levels. Because the transition time is finite, starting the

signal transition from different voltage levels causes

timing jitter. The time constant for an AC-coupled link

needs to be chosen to reduce droop and jitter to an

acceptable level.

The RC network for an AC-coupled link consists of the

LVDS receiver termination resistor (RT), the LVDS driver

output resistor (RO), and the series AC-coupling capac-

itors (C). The RC time constant for two equal-value

series capacitors is (C x (RT + RO)) / 2 (Figure 10). The

RC time constant for four equal-value series capacitors

is (C x (RT + RO)) / 4 (Figure 11).

RT is required to match the transmission line imped-

ance (usually 100Ω) and RO is determined by the LVDS

driver design (the minimum differential output resis-

tance of 78Ω for the MAX9209/MAX9211/MAX9213/

MAX9215 serializers is used in the following example).

This leaves the capacitor selection to change the sys-

tem time constant.

+

-

RxCLK IN

CYCLE N - 1

CYCLE N

DCA2

RxIN2

DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCA2

CYCLE N + 1

DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14

DCA1

RxIN1

DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9

TxIN8

TxIN7

DCA1

DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9

TxIN8

TxIN7

DCA0

RxIN0

DCB0

TxIN6

TxIN5

TxIN4

TxIN3

TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.

TxIN2

TxIN1

TxIN0

DCA0

DCB0

TxIN6

TxIN5

TxIN4

TxIN3

TxIN2

TxIN1

TxIN0

Figure 9. Deserializer Serial Input

Maxim Integrated

9

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