MAX9949(2009) データシートの表示（PDF） - Maxim Integrated
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MAX9949 Datasheet PDF : 23 Pages
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Dual Per-Pin Parametric Measurement Units
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, VEE = -7V, VL = +3.3V, CCM = 120pF, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. TA < +25°C guaranteed
by design and characterization. Typical values are at TA = +25°C, unless otherwise specified.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DISABLE True (0) to High-Z
CLCOMP = 20pF, measured from 50% of
digital input voltage to 10% of output
voltage
300
ns
DISABLE False (1) to Active
CLCOMP = 20pF, measured from 50% of
digital input voltage to 90% of output
voltage
100
ns
SERIAL PORT (VL = +3.0V, CDOUT = 10pF)
Serial Clock Frequency
fSCLK
20
MHz
SCLK Pulse-Width High
tCH
12
ns
SCLK Pulse-Width Low
tCL
12
ns
SCLK Fall to DOUT Valid
CS Low to SCLK High Setup
SCLK High to CS High Hold
SCLK High to CS Low Hold
CS High to SCLK High Setup
tDO
tCSS0
tCSH1
tCSH0
tCSS1
22
ns
10
ns
22
ns
0
ns
5
ns
DIN to SCLK High Setup
tDS
10
ns
DIN to SCLK High Hold
CS Pulse-Width High
CS Pulse-Width Low
LOAD Pulse-Width Low
VDD High to CS Low (Power-Up)
tDH
tCSWH
tCSWL
tLDW
(Note 14)
(Note 14)
0
ns
10
ns
10
ns
20
ns
500
µs
Note 2: The device operates properly with different supply voltages with equally different voltage swings.
Note 3: Tested at VCC = +18V and VEE = -12V.
Note 4: Interpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point to end-point
range, i.e., for the ±25mA range, the full-scale range = 50mA and a 1% error = 500µA.
Note 5: Case must be maintained ±5°C for linearity specifications.
Note 6: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled.
Note 7: Tested in range C.
Note 8: Linearity of the measured output is only guaranteed within the specified current range.
Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at VL adjusts the threshold.
Note 10: Settling times are to 0.1% of FSR. Cx = 47pF.
Note 11: All settling times are specified using a single compensation capacitor (Cx) across all current-sense resistors. Use an indi-
vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges.
Note 12: The actual settling time of the measured voltage path (SENSE_ input to MSR_ output) is less than 1µs. However, the R-C
time constant of the sense resistor and the load capacitance causes a longer overall settling time of the DUT voltage. This
settling time is a function of the current-range resistor used.
Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by
holding the SENSE_ input voltage steady and transitioning THMAX_ or THMIN_.
Note 14: Guaranteed by design.
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