MBM29LV008BA-12 データシートの表示（PDF） - Fujitsu

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MBM29LV008BA-12

FLASH MEMORY CMOS 8M (1M × 8) BIT

Fujitsu 

MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12

Table 7 MBM29LV008TA/BA Extended Command Definitions

Command

Sequence

Bus Write

Cycles

Req'd

First Bus

Write Cycle

Addr Data

Second Bus

Write Cycle

Addr Data

Third Bus

Write Cycle

Addr Data

Fourth Bus

Read Cycle

Addr Data

Set to

Fast Mode

3

555H AAH 2AAH 55H 555H 20H

—

—

Fast Program

*1

2

XXXH A0H

PA

PD

—

—

—

—

Reset from Fast

Mode *1

2

XXXH

90H

XXXH

F0H

*3

—

—

—

—

Extended Sector

Protect * 2

4

XXXH 60H

SPA

60H

SPA

40H

SPA

SD

SPA: Sector address to be protected. Set sector address (SA) and (A10, A6, A1, A0) = (0, 0, 1, 0).

SD: Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected

sector addresses.

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET= VID.

*3: The data "00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the

read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The devices remain enabled for reads until the command

register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

15

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