MBM29LV008BA-12 データシートの表示（PDF） - Fujitsu

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MBM29LV008BA-12

FLASH MEMORY CMOS 8M (1M × 8) BIT

Fujitsu 

MBM29LV008TA-70/-90/-12/MBM29LV008BA-70/-90/-12

s AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

JEDEC Standard

Description

Test Setup

-70

(Note)

-90

(Note)

-12

(Note)

Unit

tAVAV

tAVQV

tRC Read Cycle Time

tACC Address to Output Delay

— Min. 70

CE = VIL

OE = VIL

Max.

70

90

120 ns

90

120 ns

tELQV

tCE Chip Enable to Output Delay

OE = VIL Max. 70

90

120 ns

tGLQV

tOE Output Enable to Output Delay

— Max. 30

35

50 ns

tEHQZ

tDF Chip Enable to Output High-Z

— Max. 25

30

30 ns

tGHQZ

tDF Output Enable to Output High-Z

— Max. 25

30

30 ns

tAXQX

Output Hold Time From

tOH Addresses,

— Min. 0

CE or OE, Whichever Occurs First

0

0

ns

—

tREADY RESET Pin Low to Read Mode

— Max. 20

20

20 µs

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29LV008TA/BA-70)

1 TTL gate and 100 pF (MBM29LV008TA/BA-90/-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output:1.5 V

Device

Under

Test

CL

3.3 V

IN3064

or Equivalent

2.7 kΩ

6.2 kΩ

Diodes = IN3064

or Equivalent

Notes: CL = 30 pF including jig capacitance (MBM29LV008TA/BA-70)

CL = 100 pF including jig capacitance (MBM29LV008TA/BA-90/-12)

Figure 4 Test Conditions

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