MC10SX1125A データシートの表示（PDF） - ON Semiconductor
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MC10SX1125A Datasheet PDF : 8 Pages
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MC10SX1125A
FUNCTION TABLE
Pin
Function
CAZN
CAZP
GNDA
Auto-zero capacitor pin. A capacitor between this pin and CAZP cancels any offset inherent to the limiting amplifier.
Auto-zero capacitor pin. A capacitor between this pin and CAZN cancels any offset inherent to the limiting amplifier.
Analog ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the
same potential.
Din, Din
VCCA
Differential data input.
Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at
the same potential.
CLD
Disable
Filter capacitor for the level detect comparator. Capacitor should be connected to VCCA.
When asserted LOW, or left open and pulled LOW via the input pulldown resistor, the output buffer will be enabled and
will respond to the input stimulus on the Din input. Forcing Disable HIGH will force the Dout output LOW and its
complimentary output HIGH.
LOS
GNDE
Loss of signal. This output will go HIGH when the input signal falls below (Vset/100) mVP-P.
Digital ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the
same potential.
Dout, Dout
VCCE
Differential data outputs.
Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the
same potential.
Vref
Vset
Reference voltage for threshold level set voltage division network (2.64V).
Input threshold level detect setting input. Input generated from voltage divider between Vref and GNDA.
CAZ
Cin
DATA IN Cin
5V
Cbypass
CAZ
1 CAZN
2 CAZP
3 GNDA
4 Din
5 Din
6 VCCA
7 CLD
8 Disable
Vset 16
R1
R2
Vref 15
VCCE 14
Dout 13
Dout 12
GNDE 11
LOS 10
LOS 9
50
DATA OUT
50
50
LEVEL
DETECT OUT
50
5V
Cbypass
3V
Figure 1. Typical Operating Circuit
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