NLV14011BDR2G データシートの表示（PDF） - ON Semiconductor

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NLV14011BDR2G

B-Suffix Series CMOS Gates

ON Semiconductor 

MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,

MC14025B, MC14071B, MC14073B,

MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired.

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range.

• Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

• Pin−for−Pin Replacements for Corresponding CD4000 Series

B Suffix Devices

• These Devices are Pb−Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

Vin, Vout

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

−0.5 to +18.0

V

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

± 10

mA

PD Power Dissipation, per Package

(Note 1)

500

mW

TA

Ambient Temperature Range

Tstg Storage Temperature Range

TL

Lead Temperature

(8−Second Soldering)

−55 to +125

°C

−65 to +150

°C

260

°C

VESD ESD Withstand Voltage

V

Human Body Model

> 3000

Machine Model

> 300

Charged Device Model

N/A

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

14

MC140xxBCP

AWLYYWWG

1

14

SOIC−14

D SUFFIX

CASE 751A

140xxBG

AWLYWW

1

14

TSSOP−14

DT SUFFIX

CASE 948G

14

0xxB

ALYWG

G

1

xx

A

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

WW, W = Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

DEVICE INFORMATION

Device

MC14001B

MC14011B

MC14023B

MC14025B

MC14071B

MC14073B

Description

Quad 2−Input NOR Gate

Quad 2−Input NAND Gate

Triple 3−Input NAND Gate

Triple 3−Input NOR Gate

Quad 2−Input OR Gate

Triple 3−Input AND Gate

MC14081B

MC14082B

Quad 2−Input AND Gate

Dual 4−Input AND Gate

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

© Semiconductor Components Industries, LLC, 2013

1

April, 2013 − Rev. 10

Publication Order Number:

MC14001B/D

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