NLV14081BDG データシートの表示（PDF） - ON Semiconductor

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NLV14081BDG

B-Suffix Series CMOS Gates

ON Semiconductor 

MC14001B Series

TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

SINGLE INPUT NAND, AND

5.0

MULTIPLE INPUT NOR, OR

4.0

SINGLE INPUT NOR, OR

3.0

MULTIPLE INPUT NAND, AND

2.0

1.0

0

0 1.0 2.0 3.0 4.0 5.0

Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc

SINGLE INPUT NAND, AND

10

MULTIPLE INPUT NOR, OR

8.0

SINGLE INPUT NOR, OR

6.0

MULTIPLE INPUT NAND, AND

4.0

2.0

0

0 2.0 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (Vdc)

Figure 9. VDD = 10 Vdc

16

SINGLE INPUT NAND, AND

14

MULTIPLE INPUT NOR, OR

12

SINGLE INPUT NOR, OR

10

MULTIPLE INPUT NAND, AND

8.0

6.0

4.0

2.0

0

0 2.0 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

DC NOISE MARGIN

The DC noise margin is defined as the input voltage range

from an ideal “1” or “0” input level which does not produce

output state change(s). The typical and guaranteed limit

values of the input values VIL and VIH for the output(s) to

be at a fixed voltage VO are given in the Electrical

Characteristics table. VIL and VIH are presented graphically

in Figure 11.

Guaranteed minimum noise margins for both the “1” and

“0” levels =

1.0 V with a 5.0 V supply

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

Vout

VDD

VO

Vout

VDD

VO

VO

VO

VDD

VDD

0

Vin

0

Vin

VIL

VIH

(a) Inverting Function

VSS = 0 VOLTS DC

VIL

VIH

(b) Non−Inverting Function

Figure 11. DC Noise Immunity

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