MK2042-01 データシートの表示（PDF） - Integrated Circuit Systems
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MK2042-01 Datasheet PDF : 6 Pages
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ADVANCE INFORMATION
MK2042-01
I CR O C LOC K
Communications Clock Monitor
Pin Assignment
S0 1
S1 2
S2 3
INB 4
INA 5
GND 6
SELB 7
REFIN 8
16 OE
15 VDD
14 CLKOUT
13 NO_INA
12 HIGH
11 LOW
10 GND
9 CENTER
16 pin (150 mil) SOIC
Clock Loss Detector Settings
S2 S1 S0 Nominal Count
000
34
001
18
010
130
011
66
100
10
101
6
110
2
111
2
Due to the possible phase differences between
the REFIN clock and the INA clock, the
Nominal Count has a tolerance of -0/+1
REFIN clock edges.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
S0
S1
S2
INB
INA
GND
SELB
REFIN
CENTER
GND
LOW
HIGH
NO_INA
CLKOUT
VDD
OE
Type Description
I Clock Count Select 0. Determines allowed number of missing clock edges per table above.
I Clock Count Select 1. Determines allowed number of missing clock edges per table above.
I Clock Count Select 2. Determines allowed number of missing clock edges per table above.
I Input Clock B.
I Input Clock A.
P Connect to ground.
I Mux select. Selects INB when high.
I Reference Clock Input.
I Enables HIGH and LOW pins when high.
P Connect to ground.
O Sets low end of centering range.
O Sets high end of centering range.
O Goes high when clock on INA stops.
O Clock output.
P Connect to +3.3 V or +5 V.
I Output Enable. Tri-states CLKOUT when low.
Type: I = Input, O = output, P = power supply connection
All inputs have an internal pull-up.
MDS 2042-01
2
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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