MK2049-01 データシートの表示（PDF） - Integrated Circuit Systems

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MK2049-01

Communications Clock PLL

Integrated Circuit Systems 

MK2049-01

Communications Clock PLL

LAYOUT AND EXTERNAL COMPONENTS (continued)

Loop Filter Components

The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 2 below, and as

close to the chip as possible. Be sure to follow the recommendations on capacitor types described on page 6.

CAP2

1.5 nF

CAP1

7.5 MΩ

0.030 µF

Figure 2. Loop Filter component values for most configurations

Typical component values are shown. Contact the ICS MicroClock applications

department at (408)297-1201 for the recommended values for your application.

Crystal Operation

The MK2049 operates by phase locking the input signal to a VCXO which consists of the special

recommended crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best

performance and reliability, the layout guidelines shown on the previous page must be closely followed.

The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected

to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal.

External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To

achieve this, the layout should use short traces between the MK2049 and the crystal.

MDS 2049-01 J

6

Revision 040601

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com

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