MK2771-12 データシートの表示（PDF） - Integrated Circuit Systems
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MK2771-12 Datasheet PDF : 4 Pages
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I CR O C LOC K
MK2771-12
VCXO and Set-Top Clock Source
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5 V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
DC CHARACTERISTICS (VDD = 5.0V unless noted)
150
°C
Operating Voltage, VDD
4.75
5.25
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH (except PCS1)
2
V
Input Low Voltage, VIL (except PCS1)
0.8
V
Input High Voltage, VIH, PCS1 only
VDD-0.5
V
Input Low Voltage, VIL, PCS1 only
0.5
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
60
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
7
pF
Frequency synthesis error
All clocks
0
ppm
VIN, VCXO control voltage
0
AC CHARACTERISTICS (VDD = 5.0V unless noted)
3
V
Input Frequency
13.50000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
200
ps
Skew of 27 MHz outputs
Rising edges at 1.4V
-500
0
500
ps
27 MHz output pullability, note 3
0V ≤ VIN ≤ 3V
±100
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With PCLK at 50 MHz.
3. With a pullable crystal that conforms to ICS’ specifications.
External Components
The MK2771-12 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND, and betweeen AVDD and GND,
as close to the MK2771-12 as possible. A series termination resistor of 33 Ω may be used for each clock
output.The 13.5 MHz crystal must be connected as close to the chip as possible. The 13.5 MHz crystal
should be a parallel mode, pullable, with load capacitance of 16 pF. Consult MicroClock for recommended
suppliers. Only the crystal should be connected to X1 and X2; do not connect load capacitors to these pins.
MDS 2771-12 A
3
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
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