MT3171BE1 データシートの表示（PDF） - Zarlink Semiconductor Inc
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MT3171BE1 Datasheet PDF : 15 Pages
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MT3170B/71B, MT3270B/71B, MT3370B/71B
Data Sheet
Pin Description
337xB
15
Pin #
327xB
7
18
8
1,5,7,8,
-
10, 12,
14,16,
17
3
-
317xB
7
Name
Description
ESt Early Steering Output. A logic high on ESt indicates that a DTMF
(MT3x70B) signal is present. ESt is at logic low in powerdown state.
DStD Delayed Steering Output. A logic high on DStD indicates that a
(MT3x71B) valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
8
VDD Positive Power Supply (5 V Typ.) Performance of the device can
be optimized by minimizing noise on the supply rails. Decoupling
capacitors across VDD and VSS are therefore recommended.
-
NC No Connection. Pin is unconnected internally.
2
PWDN Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
Device
Type
MT3170B
MT3171B
MT3270B
MT3271B
MT3370B
MT3371B
Summary of MT3x70/71B Product Family
8 Pin
18 Pin
20 Pin PWDN
2 Pin
OSC
Ext
CLK
ESt
DStD
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Functional Description
The MT3x7xBs are high performance and low power consumption DTMF receivers. These devices provide wide
dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy
detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the
unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is
routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to
separate the input DTMF signal into high and low group tones. The high group and low group tones are then
verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection
stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be
shifted out serially by applying external clock pulses.
Automatic Gain Control (AGC) Circuit
As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With
large input signal amplitude (between 0 and approximately -30 dBm for each tone of the composite signal), the
3
Zarlink Semiconductor Inc.
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