MT46V128M4TG-8 データシートの表示（PDF） - Micron Technology

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MT46V128M4TG-8

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The

most recently registered READ command prior to the

BURST TERMINATE command will be truncated, as

shown in the Operation section of this data sheet. The

open page which the READ burst was terminated from

remains open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the DDR SDRAM and is analogous to CAS#-BEFORE-

RAS# (CBR) REFRESH in FPM/EDO DRAMs. This com-

mand is nonpersistent, so it must be issued each time

a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits a “Don’t Care”

during an AUTO REFRESH command. The 512Mb DDR

SDRAM requires AUTO REFRESH cycles at an average

interval of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-

lute refresh interval is provided. A maximum of eight

AUTO REFRESH command can be posted to any given

DDR SDRAM, meaning that the maximum absolute

interval between any AUTO REFRESH command and

the next AUTO REFRESH command is 9 × 7.8125µs

(70.3µs). This maximum absolute interval is to allow

ADVANCE

512Mb: x4, x8, x16

DDR SDRAM

future support for DLL updates internal to the DDR

SDRAM to be restricted to AUTO REFRESH cycles, with-

out allowing excessive drift in tAC between updates.

Although not a JEDEC requirement, to provide for

future functionality features, CKE must be active

(High) during the AUTO REFRESH period. The AUTO

REFRESH period begins when the AUTO REFRESH

command is registered and ends tRFC later.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system

is powered down. When in the self refresh mode, the

DDR SDRAM retains data without external clocking.

The SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW). The

DLL is automatically disabled upon entering SELF RE-

FRESH and is automatically enabled upon exiting SELF

REFRESH (200 clock cycles must then occur before a

READ command can be issued). Input signals except

CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a se-

quence of commands. First, CK must be stable prior to

CKE going back HIGH. Once CKE is HIGH, the DDR

SDRAM must have NOP commands issued for tXSNR

because time is required for the completion of any in-

ternal refresh in progress. A simple algorithm for meet-

ing both refresh and DLL requirements is to apply NOPs

for 200 clock cycles before applying any other com-

mand.

512Mb: x4, x8, x16 DDR SDRAM

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

15

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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