MT46V128M4TG-8L データシートの表示（PDF） - Micron Technology
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MT46V128M4TG-8L Datasheet PDF : 68 Pages
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ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
ADDRESS
DQS
DQ
CK#
CK
COMMAND
ADDRESS
DQS
T0
READ
Bank,
Col n
T0
READ
Bank,
Col n
T1
T2 T2n T3 T3n T4
NOP
NOP
READ
NOP
CL = 2
Bank,
Col b
DO
n
T1
T2 T2n T3 T3n T4
NOP
NOP
READ
NOP
CL = 2.5
Bank,
Col b
T5 T5n T6
NOP
NOP
DO
b
T5 T5n T6
NOP
NOP
DQ
DO
DO
n
b
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
Figure 9
Nonconsecutive READ Bursts
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
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©2001, Micron Technology, Inc.
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