MT46V128M4TG-8 データシートの表示（PDF） - Micron Technology

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MT46V128M4TG-8

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

ADVANCE

512Mb: x4, x8, x16

DDR SDRAM

PIN DESCRIPTIONS

TSOP PIN NUMBERS SYMBOL

45, 46

CK, CK#

44

CKE

24

CS#

23, 22, 21

47

20, 47

RAS#, CAS#,

WE#

DM

LDM, UDM

26, 27

29-32, 35-40,

28, 41, 42

BA0, BA1

A0–A12

2, 4, 5, 7, 8, 10, 11, 13,

54, 56, 57, 59, 60, 62,

63, 65

DQ0–15

TYPE

Input

Input

Input

Input

Input

Input

Input

I/O

DESCRIPTION

Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS) is referenced to the crossings of CK and CK#.

Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers and output drivers. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH

operations (all banks idle), or ACTIVE POWER-DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER-DOWN

entry and exit, and for SELF REFRESH entry. CKE is asynchronous

for SELF REFRESH exit and for disabling the outputs. CKE must be

maintained HIGH throughout read and write accesses. Input

buffers (excluding CK, CK# and CKE) are disabled during POWER-

DOWN. Input buffers (excluding CKE) are disabled during SELF

REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS

LOW level after VDD is applied.

Chip Select: CS# enables (registered LOW) and disables (regis-

tered HIGH) the command decoder. All commands are masked

when CS# is registered HIGH. CS# provides for external bank

selection on systems with multiple banks. CS# is considered part

of the command code.

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

command being entered.

Input Data Mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading is designed to

match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0-

DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8

Bank Address Inputs: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A10) for READ/WRITE

commands, to select one location out of the memory array in the

respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA0, BA1) or all banks (A10 HIGH). The address

inputs also provide the op-code during a MODE REGISTER SET

command. BA0 and BA1 define which mode register (mode register

or extended mode register) is loaded during the LOAD MODE

REGISTER command.

Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63

are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 for x4).

(continued on next page)

512Mb: x4, x8, x16 DDR SDRAM

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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