MT47H128 データシートの表示（PDF） - Micron Technology

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MT47H128

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Features

List of Figures

Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 8

Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 11

Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 12

Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 13

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15

Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 Die Rev :H .................................................................. 18

Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8 Die Rev :H ............................................................................... 19

Figure 10: 84-Ball FBGA Package (8mm x 12.5mm) – x16; "NF" Die Rev :M ....................................................... 20

Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev :M ................................................................... 21

Figure 12: Example Temperature Test Point Location ...................................................................................... 24

Figure 13: Single-Ended Input Signal Levels ................................................................................................... 45

Figure 14: Differential Input Signal Levels ...................................................................................................... 46

Figure 15: Differential Output Signal Levels .................................................................................................... 48

Figure 16: Output Slew Rate Load .................................................................................................................. 49

Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 50

Figure 18: Full Strength Pull-Up Characteristics .............................................................................................. 51

Figure 19: Reduced Strength Pull-Down Characteristics .................................................................................. 52

Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 53

Figure 21: Input Clamp Characteristics .......................................................................................................... 54

Figure 22: Overshoot ..................................................................................................................................... 55

Figure 23: Undershoot ................................................................................................................................... 55

Figure 24: Nominal Slew Rate for tIS ............................................................................................................... 60

Figure 25: Tangent Line for tIS ........................................................................................................................ 60

Figure 26: Nominal Slew Rate for tIH .............................................................................................................. 61

Figure 27: Tangent Line for tIH ....................................................................................................................... 61

Figure 28: Nominal Slew Rate for tDS ............................................................................................................. 66

Figure 29: Tangent Line for tDS ...................................................................................................................... 66

Figure 30: Nominal Slew Rate for tDH ............................................................................................................. 67

Figure 31: Tangent Line for tDH ..................................................................................................................... 67

Figure 32: AC Input Test Signal Waveform Command/Address Balls ................................................................ 68

Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 68

Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 69

Figure 35: AC Input Test Signal Waveform (Differential) .................................................................................. 69

Figure 36: MR Definition ............................................................................................................................... 77

Figure 37: CL ................................................................................................................................................. 80

Figure 38: EMR Definition ............................................................................................................................. 81

Figure 39: READ Latency ............................................................................................................................... 84

Figure 40: WRITE Latency .............................................................................................................................. 84

Figure 41: EMR2 Definition ........................................................................................................................... 85

Figure 42: EMR3 Definition ........................................................................................................................... 86

Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 87

Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 90

Figure 45: Multibank Activate Restriction ....................................................................................................... 91

Figure 46: READ Latency ............................................................................................................................... 93

Figure 47: Consecutive READ Bursts .............................................................................................................. 94

Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 95

Figure 49: READ Interrupted by READ ............................................................................................................ 96

Figure 50: READ-to-WRITE ............................................................................................................................ 96

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

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