MT47H128 データシートの表示（PDF） - Micron Technology

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MT47H128

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

State Diagram

Figure 2: Simplified State Diagram

1Gb: x4, x8, x16 DDR2 SDRAM

State Diagram

OCD

default

Setting

MRS

EMRS

(E)MRS

Initialization

sequence

PRE

Idle

all banks

precharged

SR

CKE_H

CKE_L

Self

refreshing

REFRESH

Refreshing

CKE_H CKE_L

CKE_L

Automatic Sequence

Command Sequence

ACT

CKE_L

Active

power-

down

CKE_L

Activating

CKE_CLKE_H

Bank

active

Precharge

power-

down

CKE_L

ACT = ACTIVATE

CKE_H = CKE HIGH, exit power-down or self refresh

CKE_L = CKE LOW, enter power-down

(E)MRS = (Extended) mode register set

PRE = PRECHARGE

PRE_A = PRECHARGE ALL

READ = READ

READ A = READ with auto precharge

REFRESH = REFRESH

SR = SELF REFRESH

WRITE = WRITE

WRITE A = WRITE with auto precharge

WRITE

WRITE

READ

READ

Writing

WRITE

READ

Reading

WRITE A

READ A

WRITE A

READ A

Writing

with

auto

precharge

PRE, PRE_A

Precharging

Reading

with

auto

precharge

Note: 1. This diagram provides the basic command flow. It is not comprehensive and does not

identify all timing requirements or possible command restrictions such as multibank in-

teraction, power down, entry/exit, etc.

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

8

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

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