PDM41024SA10TA データシートの表示（PDF） - Unspecified

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PDM41024SA10TA

1 Megabit Static RAM 128K x 8-Bit

Unspecified 

Features

n High-speed access times

Com’l: 10, 12 and 15 ns

Ind’l: 12 and 15 ns

n Low power operation (typical)

- PDM41024SA

Active: 450 mW

Standby: 50 mW

- PDM41024LA

Active: 400 mW

Standby: 25mW

n Single +5V (±10%) power supply

n TTL-compatible inputs and outputs

n Packages

Plastic SOJ (300 mil) - TSO

Plastic SOJ (400 mil) - SO

Plastic TSOP (I)- T

PDM41024

Description

1 Megabit Static RAM

128K x 8-Bit

1

2 The PDM41024 is a high-performance CMOS static

RAM organized as 131,072 x 8 bits. Writing is

accomplished when the write enable (WE) and the

chip enable (CE1) inputs are both LOW and CE2 is

3 HIGH. Reading is accomplished when WE and CE2

remain HIGH and CE1 and OE are both LOW.

The PDM41024 operates from a single +5V power

supply and all the inputs and outputs are fully TTL-

4 compatible. The PDM41024 comes in two versions:

the standard power version (SA) and the low power

version (LA). The two versions are functionally the

same and differ only in their power consumption.

5 The PDM41024 is available in a 32-pin plastic TSOP

(I), and a 300-mil and 400-mil plastic SOJ.

6

Functional Block Diagram

A0

•

•

Addresses

•

•

•

A16

I/O 0

•

•

I/O 7

CE1

CE2

WE

OE

Control

Decoder

Input

Data

Control

• Memory

•

•

•

Matrix

•

•

•••••

Column I/O

•

•

•

7

8

9

10

11

12

Rev. 3.3 - 4/09/98

1

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