PDM41024SA10TA データシートの表示（PDF） - Unspecified
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PDM41024SA10TA Datasheet PDF : 8 Pages
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PDM41024
Write Cycle No. 3 (Chip Enable Controlled)
tWC
1
ADDR
tAW
tAH
tAS
tCW
2
CE2
CE1
tWP1
3
WE
DIN
tDS
tDH
DATA VALID
4
DOUT
HIGH-Z
NOTE: Output Enable (OE) is inactive (high)
5
AC Electrical Characteristics
Description
-10(7)
-12(7)
-15
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
tWC
10
12
15
ns
Chip enable active time
tCW
10
10
11
ns
Address valid to end of write
tAW
10
10
11
ns
Address setup time
tAS
0
0
0
ns
Address hold from end of write
tAH
0
0
0
ns
Write pulse width
tWP1
8
8
11
ns
Write pulse width
tWP2
8
8
12
ns
Data setup time
tDS
7
7
7
ns
Data hold time
tDH
0
0
0
ns
Write disable to output in low Z(1,3)
tLZWE
0
0
0
ns
Write enable to output in high Z(1,3) tHZWE
7
7
7 ns
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table
6
7
8
9
10
11
12
Rev. 3.3 - 4/09/98
7
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