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PJ494CD

Switchmode Pulse Width Modulation Control Circuit

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PJ494

Switchmode Pulse Width Modulation Control Circuit

APPLICATIONS INFORMATION

Description

The PJ494 is a fixed-frequency pulse width modulation control circuit, incorporating the primary building blocks required for

the control of a switching power supply . (See Figure 1.) An internal-linear sawtooth oscillator is frequescy-programmable by two

external components, RT and CT. The approximate oscillator frequency is determined by:

……….. For more information refer to Figure 3.

Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to

either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip-flop

clock-input line is in its low state. This happens only during that portion of time when the sawtoothvoltage is greater than the

control signals. Therefore, an increase in contro-signal amplitude causes a corresponding linear decrease of output pulse width.

(Refer to the Timing Diagram shown in Figure 2.)

The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback

input. The deadtime control comparator has an effective 120mV input offset which limits the minimum output deadtime to

approximately tge first 4% of the sawtooth-cycle time. This would result in a maximum duty cycle on a given output of 96% with

the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output

by setting the deadtime-control input to a fixed voltage, ranging between 0V to 3.3V .

The pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the

maximum percent on-time, established by the deadtime control input, down to zero as the voltage at the feedback pin varies from

0.5V to 3.5V. Both error amplifiers have a common mode input range from -0.3C to (Vcc – 2V), and may be ised to sense power-

supply output voltage and current. The error –amplifier outputs are active high and are ORed together at the noninverting input of

the pulse-width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates

control of the loop.

When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the

pulse-steering flip=flop and inhibits the output transistors, Q1 and Q2. With the output-control connected to the reference line, the

pulse-steering flip-flop directs the modulated pulses to each of the rwo output transistors alternately for push-pull operation. The

output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 and Q2, when single-ended

operation with a maximum on-time of less than 50% is required. This is desirable when the output transformer has a ringback

winding with a catch diode ised for snubbing. When higher output-drive currents are required for single-ended operation, Q1 and

Q2 may be connected in parallel, and the output mode pin must be tied to ground to disable the flip-flop. The output frequency

will now be equal to that of the oscillator.

The PJ494 has an internal 5.0V reference capable of sourcing up to 10mA of laod current for external bias circuits. The

reference has an internal accuracy of ±5.0% with a typical thermal drift of less than 50mV over an operating temperature range of 0 to

70℃.

Figure 3. Oscillator Frequency versus Timing Resistance

5-11

2002/11.rev.A

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