QL8025 データシートの表示（PDF） - Unspecified

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QL8025

Low Power FPGA Combining Performance, Density, and Embeded RAM

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The Eclipse-II logic cell structure is presented in )LJXUH . This architectural feature addresses

today's register-intensive designs.

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Multiplexer

16:1

5 ns

2.8 ns

Parity Tree

24

6 ns

3.4 ns

Counter

36

6 ns

3.4 ns

16 bit

250 MHz

450 MHz

32 bit

250 MHz

450 MHz

FIFO

128 x 32

155 MHz

280 MHz

256 x 16

155 MHz

280 MHz

128 x 64

155 MHz

280 MHz

Clock-to-Out

4.5 ns

2.5 ns

System clock

200 MHz

400 MHz

The Eclipse-II logic cell structure presented in )LJXUH  is a dual register, multiplexor-based logic

cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share

CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its

input. The register can be loaded from the NZ output or directly from a dedicated input.

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The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-

to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell

has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17

simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic

capacity and fan-in of the logic cell accommodates many user functions with a single level of logic

delay while other architectures require two or more levels of delay.

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