QL8025 データシートの表示（PDF） - Unspecified

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QL8025

Low Power FPGA Combining Performance, Density, and Embeded RAM

Unspecified 

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QS

A1

A2

A3

A4

AZ

A5

A6

OS

OP

B1

B2

C1

OZ

C2

MP

MS

QZ

D1

D2

E1

E2

NP

NZ

NS

Q2Z

F1

F2

F3

F4

FZ

F5

F6

PS

PP

QC

QR

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The Eclipse-II Product Family includes up to 24 dual-port 2,304-bit RAM modules for

implementing RAM, ROM, and FIFO functions. Each module is user-configurable into four

different block organizations and can be cascaded horizontally to increase their effective width, or

vertically to increase their effective depth as shown in )LJXUH .

2,304-bit RAM Module

MODE[1:0] ASYNCRD

WA[9:0]

RA[9:0]

WD[17:0]

RD[17:0]

WE

RE

WCLK

RCLK

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The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of

RAM. Using two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256

x 9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily

cascadable to increase their effective width and/or depth (see )LJXUH ).



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