R8A77301 データシートの表示（PDF） - Renesas Electronics

部品番号

コンポーネント説明

メーカー

R8A77301

32-Bit RISC Microcomputer

Renesas Electronics 

Section 7 Memory Management Unit (MMU) ..................................................147

7.1 Overview of MMU ........................................................................................................... 148

7.1.1 Address Spaces ......................................................................................................... 150

7.2 Register Descriptions........................................................................................................ 156

7.2.1 Page Table Entry High Register (PTEH) .................................................................. 157

7.2.2 Page Table Entry Low Register (PTEL) ................................................................... 158

7.2.3 Translation Table Base Register (TTB) .................................................................... 159

7.2.4 TLB Exception Address Register (TEA) .................................................................. 160

7.2.5 MMU Control Register (MMUCR) .......................................................................... 160

7.2.6 Page Table Entry Assistance Register (PTEA)......................................................... 164

7.2.7 Physical Address Space Control Register (PASCR)................................................. 164

7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) .......................................... 166

7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)........................................... 168

7.3.1 Unified TLB (UTLB) Configuration ........................................................................ 168

7.3.2 Instruction TLB (ITLB) Configuration..................................................................... 171

7.3.3 Address Translation Method..................................................................................... 171

7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) .............................................. 174

7.4.1 Unified TLB (UTLB) Configuration ........................................................................ 174

7.4.2 Instruction TLB (ITLB) Configuration..................................................................... 177

7.4.3 Address Translation Method..................................................................................... 178

7.5 MMU Functions................................................................................................................ 181

7.5.1 MMU Hardware Management.................................................................................. 181

7.5.2 MMU Software Management ................................................................................... 181

7.5.3 MMU Instruction (LDTLB)...................................................................................... 182

7.5.4 Hardware ITLB Miss Handling ................................................................................ 184

7.5.5 Avoiding Synonym Problems ................................................................................... 185

7.6 MMU Exceptions.............................................................................................................. 187

7.6.1 Instruction TLB Multiple Hit Exception................................................................... 187

7.6.2 Instruction TLB Miss Exception............................................................................... 188

7.6.3 Instruction TLB Protection Violation Exception ...................................................... 189

7.6.4 Data TLB Multiple Hit Exception ............................................................................ 190

7.6.5 Data TLB Miss Exception ........................................................................................ 190

7.6.6 Data TLB Protection Violation Exception................................................................ 192

7.6.7 Initial Page Write Exception..................................................................................... 192

7.7 Memory-Mapped TLB Configuration .............................................................................. 195

7.7.1 ITLB Address Array ................................................................................................. 196

7.7.2 ITLB Data Array (TLB Compatible Mode).............................................................. 197

7.7.3 ITLB Data Array (TLB Extended Mode) ................................................................. 198

7.7.4 UTLB Address Array................................................................................................ 200

Rev. 1.00 Sep. 19, 2007 Page xi of xlviii

Share Link: