R8A77301 データシートの表示（PDF） - Renesas Electronics

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R8A77301

32-Bit RISC Microcomputer

Renesas Electronics 

Contents

Section 1 Overview................................................................................................1

1.1 Features of This LSI ............................................................................................................. 1

1.2 Block Diagram...................................................................................................................... 9

1.3 Pin Assignments ................................................................................................................. 10

1.3.1 Pin Function................................................................................................................ 19

1.4 Product Lineup.................................................................................................................... 27

Section 2 Programming Model ............................................................................29

2.1 Data Formats....................................................................................................................... 29

2.2 Register Descriptions.......................................................................................................... 30

2.2.1 Privileged Mode and Banks ........................................................................................ 30

2.2.2 General Registers........................................................................................................ 34

2.2.3 Floating-Point Registers ............................................................................................. 35

2.2.4 Control Registers ........................................................................................................ 37

2.2.5 System Registers......................................................................................................... 39

2.3 Memory-Mapped Registers ................................................................................................ 43

2.4 Data Formats in Registers................................................................................................... 44

2.5 Data Formats in Memory .................................................................................................... 44

2.6 Processing States................................................................................................................. 45

2.7 Usage Notes ........................................................................................................................ 47

2.7.1 Notes on Self-Modifying Code................................................................................... 47

Section 3 Instruction Set ......................................................................................49

3.1 Execution Environment ...................................................................................................... 49

3.2 Addressing Modes .............................................................................................................. 51

3.3 Instruction Set ..................................................................................................................... 56

Section 4 Pipelining .............................................................................................69

4.1 Pipelines.............................................................................................................................. 69

4.2 Parallel-Executability.......................................................................................................... 80

4.3 Issue Rates and Execution Cycles....................................................................................... 83

Section 5 Exception Handling .............................................................................93

5.1 Summary of Exception Handling........................................................................................ 93

5.2 Register Descriptions.......................................................................................................... 93

5.2.1 TRAPA Exception Register (TRA) ............................................................................ 94

Rev. 1.00 Sep. 19, 2007 Page ix of xlviii

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