SCM69C433TQ15 データシートの表示（PDF） - Motorola => Freescale
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SCM69C433TQ15 Datasheet PDF : 24 Pages
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Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
42 – 44
A2 – A0
Input
3–bit control port address bus.
58
DTACK
Output Control port data transfer acknowledge (Open Drain).
17 – 20, 23 – 26,
29 – 32, 35 – 38
DQ15 – DQ0
I/O
16–bit bidirectional control port data bus.
61
G
Input
Output Enable control of MQ31 – MQ0.
57
IRQ
Output Control port interrupt (Open Drain).
39
K
Input
Interface Clock, max frequency of 66 MHz.
47
89
92
64
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
1, 2, 5 – 8, 11 – 14
62
56
46
52
50
55
51
49
KMODE
C. LH/SM
R, IN LL
CTO MC
ONDU MQ31 – MQ0
Input
Input
Input
Output
I/O
See Note.
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
Latch Low. Latches low order bits if match width is > 32 bits.
Match Complete (Open Drain).
32–bit common I/O CAM data. Used for input of match RAM and data RAM
values.
E SEMIC MS
AL RESET
ESC SEL
FRE TCK
BY TDI
ED TDO
HIV TMS
ARCTRST
Output
Input
Input
Input
Input
Output
Input
Input
Match Successful (Open Drain).
Resets chip to a known state.
Control port chip select, active low.
Test Clock, part of JTAG interface.
Test Data In, part of JTAG interface.
Test Data Out, part of JTAG interface.
Test Mode Select, part of JTAG interface.
Tap Reset part of JTAG interface.
63
VPC
Output Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
45
WE
Input
Control port Write Enable.
4, 10, 16, 22, 27, 33,
41, 48, 54, 59, 65, 71,
77, 84, 91, 97
VDD
Supply Power Supply: 3.3 V ±5%.
3, 9, 15, 21, 28, 34,
40, 53, 60, 66, 72,
78, 83, 90, 98
VSS
Supply Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C433•SCM69C433
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